Searched +full:0 +full:x10048000 (Results 1 – 7 of 7) sorted by relevance
58 reg = <0x10048000 0x1000>;
31 reg = <0x10030000 0x20000>;37 reg = <0x105C0000 0x2000>;43 reg = <0x10048000 0x1000>;53 reg = <0x13800000 0x100>;54 interrupts = <0 109 0>;
29 reg = <0x10030000 0x20000>;39 reg = <0x13820000 0x100>;40 interrupts = <0 54 0>;75 reg = <0x10030000 0x18000>;81 reg = <0x10048000 0x1000>;
15 #size-cells = <0>;17 cpu@0 {19 reg = <0x0>;26 reg = <0x1>;33 reg = <0x2>;40 reg = <0x3>;49 #clock-cells = <0>;72 reg = <0 0x0c000000 0 0x40000>, /* GICD */73 <0 0x0c080000 0 0x200000>, /* GICR */74 <0 0x0c400000 0 0x2000>, /* GICC */[all …]
15 #size-cells = <0>;17 cpu@0 {19 reg = <0x0>;26 reg = <0x1>;36 #clock-cells = <0>;52 reg = <0 0x0c000000 0 0x40000>, /* GICD */53 <0 0x0c080000 0 0x200000>; /* GICR */62 reg = <0 0x10001000 0 0x1000>;68 reg = <0 0x1001b000 0 0x1000>;74 reg = <0 0x1001c000 0 0x1000>;[all …]
21 #size-cells = <0>;22 cpu0: cpu@0 {24 reg = <0x0>;32 reg = <0x1>;40 reg = <0x2>;48 reg = <0x3>;58 #clock-cells = <0>;73 reg = <0 0x43000000 0 0x30000>;79 reg = <0 0x4fc00000 0 0x00100000>;83 reg = <0 0x4fd00000 0 0x40000>;[all …]
70 #interconnect-cells = <0>;80 #interconnect-cells = <0>;120 #interconnect-cells = <0>;211 reg = <0x11400000 0x1000>;217 reg = <0x11000000 0x1000>;229 reg = <0x03860000 0x1000>;231 interrupts = <10 0>;[all...]