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Searched +full:0 +full:x100400 (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/i2c/
H A Dsnps,designware-i2c.yaml135 reg = <0xf0000 0x1000>;
142 reg = <0x1120000 0x1000>;
154 reg = <0x2000 0x100>;
156 #size-cells = <0>;
159 interrupts = <0>;
163 reg = <0x64>;
169 reg = <0x100400 0x100>, <0x198 0x8>;
170 pinctrl-0 = <&i2c_pins>;
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmme4_rtr_regs.h22 #define mmMME4_RTR_HBW_RD_RQ_E_ARB 0x100100
24 #define mmMME4_RTR_HBW_RD_RQ_W_ARB 0x100104
26 #define mmMME4_RTR_HBW_RD_RQ_N_ARB 0x100108
28 #define mmMME4_RTR_HBW_RD_RQ_S_ARB 0x10010C
30 #define mmMME4_RTR_HBW_RD_RQ_L_ARB 0x100110
32 #define mmMME4_RTR_HBW_E_ARB_MAX 0x100120
34 #define mmMME4_RTR_HBW_W_ARB_MAX 0x100124
36 #define mmMME4_RTR_HBW_N_ARB_MAX 0x100128
38 #define mmMME4_RTR_HBW_S_ARB_MAX 0x10012C
40 #define mmMME4_RTR_HBW_L_ARB_MAX 0x100130
[all …]
/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/linux/drivers/phy/spacemit/
H A Dphy-k3-combo.c26 * PMUA_PCIE_SUBSYS_MGMT[4:0]
28 * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A
29 * 1 : PHY lanes shared between PCIe or USB according to [3:0]
31 * All PHY matrix combinations according to [4:0]:
33 * 0x0X : PCIe-A X8
34 * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4)
35 * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4)
36 * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3)
37 * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4)
38 * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2)
[all …]
/linux/sound/pci/ctxfi/
H A Dct20k1reg.h10 #define DSPXRAM_START 0x000000
11 #define DSPXRAM_END 0x013FFC
12 #define DSPAXRAM_START 0x020000
13 #define DSPAXRAM_END 0x023FFC
14 #define DSPYRAM_START 0x040000
15 #define DSPYRAM_END 0x04FFFC
16 #define DSPAYRAM_START 0x020000
17 #define DSPAYRAM_END 0x063FFC
18 #define DSPMICRO_START 0x080000
19 #define DSPMICRO_END 0x0B3FFC
[all …]
/linux/drivers/net/fddi/
H A Ddefza.h25 #define FZA_REG_BASE 0x100000 /* register base address */
26 #define FZA_REG_RESET 0x100200 /* reset, r/w */
27 #define FZA_REG_INT_EVENT 0x100400 /* interrupt event, r/w1c */
28 #define FZA_REG_STATUS 0x100402 /* status, r/o */
29 #define FZA_REG_INT_MASK 0x100404 /* interrupt mask, r/w */
30 #define FZA_REG_CONTROL_A 0x100500 /* control A, r/w1s */
31 #define FZA_REG_CONTROL_B 0x100502 /* control B, r/w */
33 /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
34 #define FZA_RESET_DLU 0x0002 /* OR with INIT to blast flash memory */
35 #define FZA_RESET_INIT 0x0001 /* switch into the reset state */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_7_0_offset.h29 // base address: 0x50f00
30 …MCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
31 …e regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
32 …MCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
33 …e regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
34 …MCA_UMC_UMC0_MCUMC_MISC0T0 0x03c6
35 …e regMCA_UMC_UMC0_MCUMC_MISC0T0_BASE_IDX 0
36 …MCA_UMC_UMC0_MCUMC_IPIDT0 0x03ca
37 …e regMCA_UMC_UMC0_MCUMC_IPIDT0_BASE_IDX 0
38 …MCA_UMC_UMC0_MCUMC_SYNDT0 0x03cc
[all …]