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12

/linux/Documentation/devicetree/bindings/power/reset/
H A Daxxia-reset.txt14 reg = <0x20 0x10030000 0 0x2000>;
/linux/arch/mips/boot/compressed/
H A Duart-16550.c14 #define UART_BASE 0x1fd003f8
19 #define INGENIC_UART_BASE_ADDR (0x10030000 + 0x1000 * CONFIG_ZBOOT_INGENIC_UART)
33 return *((volatile IOTYPE *)PORT(offset)) & 0xFF; in serial_in()
38 *((volatile IOTYPE *)PORT(offset)) = value & 0xFF; in serial_out()
45 while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0)) in putc()
/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_cfg.h11 #define MSM_DSI_VER_MAJOR_V2 0x02
12 #define MSM_DSI_VER_MAJOR_6G 0x03
13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
14 #define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002
15 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
16 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
17 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
18 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
19 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
20 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
[all …]
/linux/arch/arm/boot/dts/intel/axm/
H A Daxm55xx.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 reg = <0x20 0x10020000 0 0x20000>;
58 #address-cells = <0>;
60 reg = <0x20 0x01001000 0 0x1000>,
61 <0x20 0x01002000 0 0x2000>,
62 <0x20 0x01004000 0 0x2000>,
63 <0x20 0x01006000 0 0x2000>;
97 reg = <0x20 0x10030000 0 0x2000>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos850-clock.yaml343 reg = <0x10030000 0x8000>;
H A Dsamsung,exynos5433-clock.yaml62 # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
507 #clock-cells = <0>;
513 reg = <0x10030000 0x1000>;
/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4770.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x40>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
58 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Djz4780.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
[all …]
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
183 reg = <0x0 0xc000000 0x0 0x4000000>;
184 #address-cells = <0>;
188 <&cpu0_intc 0xffffffff>,
189 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
190 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
191 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
[all …]
H A Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
59 reg = <0x1>;
86 reg = <0x2>;
113 reg = <0x3>;
140 reg = <0x4>;
184 #address-cells = <0>;
185 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
186 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4210.dtsi178 #size-cells = <0>;
194 reg = <0x900>;
213 reg = <0x901>;
230 bus_leftbus_opp_table: opp-table-0 {
249 reg = <0x02020000 0x20000>;
252 ranges = <0 0x02020000 0x20000>;
254 smp-sram@0 {
256 reg = <0x0 0x1000>;
261 reg = <0x1f000 0x1000>;
267 reg = <0x10023ca0 0x20>;
[all …]
H A Dexynos4x12.dtsi70 #interconnect-cells = <0>;
80 #interconnect-cells = <0>;
120 #interconnect-cells = <0>;
211 reg = <0x11400000 0x1000>;
217 reg = <0x11000000 0x1000>;
229 reg = <0x03860000 0x1000>;
231 interrupts = <10 0>;
236 reg = <0x106e0000 0x1000>;
242 reg = <0x02020000 0x40000>;
245 ranges = <0 0x02020000 0x40000>;
[all …]
H A Dexynos3250.dtsi199 #size-cells = <0>;
212 cpu0: cpu@0 {
215 reg = <0>;
259 xusbxti: clock-0 {
261 clock-frequency = <0>;
262 #clock-cells = <0>;
268 clock-frequency = <0>;
269 #clock-cells = <0>;
275 clock-frequency = <0>;
276 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos850.dtsi52 #clock-cells = <0>;
57 #size-cells = <0>;
91 cpu0: cpu@0 {
94 reg = <0x0>;
102 reg = <0x1>;
108 reg = <0x2>;
114 reg = <0x3>;
120 reg = <0x100>;
128 reg = <0x101>;
134 reg = <0x102>;
[all …]
H A Dexynos5433.dtsi48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c53 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
54 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
55 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
56 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
57 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
58 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
59 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
60 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
61 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
62 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos850.c37 /* Register Offset definitions for CMU_TOP (0x120e0000) */
38 #define PLL_LOCKTIME_PLL_MMC 0x0000
39 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
40 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
41 #define PLL_CON0_PLL_MMC 0x0100
42 #define PLL_CON3_PLL_MMC 0x010c
43 #define PLL_CON0_PLL_SHARED0 0x0140
44 #define PLL_CON3_PLL_SHARED0 0x014c
45 #define PLL_CON0_PLL_SHARED1 0x0180
46 #define PLL_CON3_PLL_SHARED1 0x018c
[all …]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192f.c18 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
19 {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01},
20 {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08},
21 {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08},
22 {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10},
23 {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00},
24 {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10},
25 {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00},
26 {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20},
27 {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e},
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x4018, 0x4F4C084B},
18 {0x401C, 0x084A4E52},
19 {0x4020, 0x4D504E4B},
[all …]

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