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/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Dmediatek,pwrap.yaml158 reg = <0 0x1000f000 0 0x1000>,
159 <0 0x11017000 0 0x1000>;
/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dhamoa.dtsi38 #clock-cells = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
58 #clock-cells = <0>;
68 #size-cells = <0>;
70 cpu0: cpu@0 {
73 reg = <0x0 0x0>;
76 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
90 reg = <0x0 0x100>;
93 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
[all …]