Searched +full:0 +full:x10008000 (Results 1 – 19 of 19) sorted by relevance
17 reg = <0x10008000 0x1000>;
43 reg = <0x10008000 0x1000>;
45 reg = <0x10008000 0x80>;
81 reg = <0x10008000 0x80>;
19 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;29 reg = <0x1>;34 reg = <0x2>;39 reg = <0x3>;47 #clock-cells = <0>;53 #clock-cells = <0>;59 #clock-cells = <0>;65 reg = <0x10008000 0x80>;[all …]
17 #size-cells = <0>;19 cpu@0 {22 reg = <0x0>;27 reg = <0x1>;32 reg = <0x2>;37 reg = <0x3>;44 #clock-cells = <0>;50 #clock-cells = <0>;56 #clock-cells = <0>;61 reg = <0x10008000 0x80>;[all …]
19 #size-cells = <0>;22 cpu@0 {25 reg = <0x0>;30 reg = <0x1>;35 reg = <0x2>;40 reg = <0x3>;54 #clock-cells = <0>;60 #clock-cells = <0>;66 #clock-cells = <0>;78 reg = <0x10008000 0x80>;[all …]
19 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;29 reg = <0x1>;34 reg = <0x2>;39 reg = <0x3>;44 reg = <0x4>;49 reg = <0x5>;54 reg = <0x6>;59 reg = <0x7>;[all …]
19 #size-cells = <0>;22 cpu@0 {25 reg = <0x0>;30 reg = <0x1>;35 reg = <0x2>;40 reg = <0x3>;52 reg = <0 0x80002000 0 0x1000>;65 #clock-cells = <0>;71 #clock-cells = <0>;77 #clock-cells = <0>;[all …]
42 #size-cells = <0>;45 cpu0: cpu@0 {48 reg = <0x000>;54 reg = <0x001>;60 reg = <0x100>;66 reg = <0x101>;77 reg = <0 0x80002000 0 0x1000>;90 #clock-cells = <0>;96 #clock-cells = <0>;101 #clock-cells = <0>;[all …]
25 #size-cells = <0>;28 cpu@0 {31 reg = <0x0>;36 reg = <0x1>;41 reg = <0x2>;46 reg = <0x3>;57 reg = <0 0x80002000 0 0x1000>;64 #clock-cells = <0>;70 #clock-cells = <0>;73 clk26m: oscillator@0 {[all …]
73 #size-cells = <0>;76 cpu0: cpu@0 {79 reg = <0x0>;91 reg = <0x1>;103 reg = <0x2>;115 reg = <0x3>;137 #clock-cells = <0>;142 #clock-cells = <0>;147 clk26m: oscillator-0 {149 #clock-cells = <0>;[all …]
43 /* 128 MiB memory @ 0x0 */44 reg = <0x00000000 0x08000000>;57 #clock-cells = <0>;63 #clock-cells = <0>;72 #clock-cells = <0>;74 clock-frequency = <0>;80 reg = <0x40000000 0x04000000>;90 reg = <0x44000000 0x04000000>;100 reg = <0x4e000000 0x10000>;110 reg = <0x4f000000 0x20000>;[all …]
24 reg = <0x0 0x08000000>;28 #clock-cells = <0>;38 #size-cells = <0>;40 port@0 {41 reg = <0>;71 reg = <0x10000000 0x200>;72 ranges = <0x0 0x10000000 0x200>;76 led@8,0 {78 reg = <0x08 0x04>;79 offset = <0x08>;[all …]
45 /* 128 MiB memory @ 0x0 */46 reg = <0x00000000 0x08000000>;67 #clock-cells = <0>;73 #clock-cells = <0>;82 #clock-cells = <0>;84 clock-frequency = <0>;89 reg = <0x30000000 0x4000000>;98 reg = <0x38000000 0x800000>;113 reg = <0x3c000000 0x4000000>;121 reg = <0x3a000000 0x10000>;[all …]
21 cluster0_opp: opp-table-0 {48 #size-cells = <0>;50 cpu0: cpu@0 {53 reg = <0x0>;66 reg = <0x1>;79 reg = <0x2>;92 reg = <0x3>;105 CPU_SLEEP_0_0: cpu-sleep-0-0 {110 arm,psci-suspend-param = <0x0010000>;113 CLUSTER_SLEEP_0: cluster-sleep-0 {[all …]
48 #size-cells = <0>;50 cpu0: cpu@0 {54 reg = <0x000>;63 reg = <0x001>;78 reg = <0x002>;93 reg = <0x003>;108 reg = <0x100>;123 reg = <0x101>;138 reg = <0x102>;153 reg = <0x10[all...]
53 cluster0_opp: opp-table-0 {129 #size-cells = <0>;151 cpu0: cpu@0 {154 reg = <0x000>;169 reg = <0x001>;184 reg = <0x100>;199 reg = <0x101>;214 CPU_SLEEP_0: cpu-sleep-0 {220 arm,psci-suspend-param = <0x0010000>;242 cpu_suspend = <0x84000001>;[all …]
47 reg = <0x10040000 0x1000>;53 #clock-cells = <0>;59 #size-cells = <0>;62 cpu: cpu@0 {64 reg = <0>;88 reg = <0x10000000 0x20000>;93 reg = <0x10001000 0x1000>;104 reg = <0x10002000 0x1000>;111 reg = <0x10003000 0x1000>;120 reg = <0x10004000 0x1000>;[all …]