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/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
H A Dmt7629.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-mt6797.txt46 Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
54 are from 0 to 15.
57 are from 0 to 63.
58 - mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
60 - mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
67 reg = <0 0x10005000 0 0x1000>,
68 <0 0x10002000 0 0x400>,
69 <0 0x10002400 0 0x400>,
70 <0 0x10002800 0 0x400>,
71 <0 0x10002C00 0 0x400>;
H A Dmediatek,mt8192-pinctrl.yaml149 reg = <0x10005000 0x1000>,
150 <0x11c20000 0x1000>,
151 <0x11d10000 0x1000>,
152 <0x11d30000 0x1000>,
153 <0x11d40000 0x1000>,
154 <0x11e20000 0x1000>,
155 <0x11e70000 0x1000>,
156 <0x11ea0000 0x1000>,
157 <0x11f20000 0x1000>,
158 <0x11f30000 0x1000>,
[all …]
H A Dpinctrl-mt8192.yaml148 reg = <0x10005000 0x1000>,
149 <0x11c20000 0x1000>,
150 <0x11d10000 0x1000>,
151 <0x11d30000 0x1000>,
152 <0x11d40000 0x1000>,
153 <0x11e20000 0x1000>,
154 <0x11e70000 0x1000>,
155 <0x11ea0000 0x1000>,
156 <0x11f20000 0x1000>,
157 <0x11f30000 0x1000>,
[all …]
H A Dpinctrl-mt65xx.txt24 Eg: <&pio 6 0>
30 - Line number: is a value between 0 to 202.
33 0 - GPIO_ACTIVE_HIGH
84 reg = <0 0x10005000 0 0x1000>;
89 reg = <0 0x1020C020 0 0x1000>;
94 reg = <0 0x1000B000 0 0x1000>;
105 i2c0_pins_a: i2c0@0 {
113 i2c1_pins_a: i2c1@0 {
121 i2c2_pins_a: i2c2@0 {
133 i2c3_pins_a: i2c3@0 {
H A Dpinctrl-mt8183.txt53 Valid arguments are from 0 to 3.
57 are from 0 to 15.
60 are from 0 to 63.
75 driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
78 When E1=0/E0=0, the strength is 0.125mA.
79 When E1=0/E0=1, the strength is 0.25mA.
80 When E1=1/E0=0, the strength is 0.5mA.
82 So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
92 reg = <0 0x10005000 0 0x1000>,
93 <0 0x11f20000 0 0x1000>,
[all …]
H A Dmediatek,mt6797-pinctrl.yaml59 '-[0-9]+$':
105 enum: [0, 1]
111 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
112 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
113 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
116 enum: [0, 1, 2, 3]
122 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
123 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
124 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
127 enum: [0, 1, 2, 3]
[all …]
H A Dmediatek,mt65xx-pinctrl.yaml141 reg = <0 0x10005000 0 0x1000>;
146 reg = <0 0x1020C020 0 0x1000>;
151 reg = <0 0x1000B000 0 0x1000>;
H A Dmediatek,mt6779-pinctrl.yaml114 '-[0-9]*$':
158 enum: [0, 1]
165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
166 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
167 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
170 enum: [0, 1, 2, 3]
177 0: (R1, R0) = (0,
[all...]
H A Dmediatek,mt6795-pinctrl.yaml136 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
137 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
138 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
141 enum: [0, 1, 2, 3]
148 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
149 1: (R1, R0) = (0,
[all...]
H A Dmediatek,pinctrl-mt6795.yaml136 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
137 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
138 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
141 enum: [0, 1, 2, 3]
147 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
148 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
149 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
152 enum: [0, 1, 2, 3]
185 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
189 gpio-ranges = <&pio 0 0 196>;
H A Dmediatek,mt8188-pinctrl.yaml188 reg = <0x10005000 0x1000>,
189 <0x11c00000 0x1000>,
190 <0x11e10000 0x1000>,
191 <0x11e20000 0x1000>,
192 <0x11ea0000 0x1000>,
193 <0x1000b000 0x1000>;
199 gpio-ranges = <&pio 0 0 176>;
201 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt8186-pinctrl.yaml229 reg = <0x10005000 0x1000>,
230 <0x10002000 0x0200>,
231 <0x10002200 0x0200>,
232 <0x10002400 0x0200>,
233 <0x10002600 0x0200>,
234 <0x10002A00 0x0200>,
235 <0x10002c00 0x0200>,
236 <0x1000b000 0x1000>;
242 gpio-ranges = <&pio 0 0 185>;
244 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt8195-pinctrl.yaml240 reg = <0x10005000 0x1000>,
241 <0x11d10000 0x1000>,
242 <0x11d30000 0x1000>,
243 <0x11d40000 0x1000>,
244 <0x11e20000 0x1000>,
245 <0x11eb0000 0x1000>,
246 <0x11f40000 0x1000>,
247 <0x1000b000 0x1000>;
253 gpio-ranges = <&pio 0 0 144>;
255 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dpinctrl-mt8186.yaml230 reg = <0x10005000 0x1000>,
231 <0x10002000 0x0200>,
232 <0x10002200 0x0200>,
233 <0x10002400 0x0200>,
234 <0x10002600 0x0200>,
235 <0x10002A00 0x0200>,
236 <0x10002c00 0x0200>,
237 <0x1000b000 0x1000>;
243 gpio-ranges = <&pio 0 0 185>;
245 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dpinctrl-mt8195.yaml241 reg = <0x10005000 0x1000>,
242 <0x11d10000 0x1000>,
243 <0x11d30000 0x1000>,
244 <0x11d40000 0x1000>,
245 <0x11e20000 0x1000>,
246 <0x11eb0000 0x1000>,
247 <0x11f40000 0x1000>,
248 <0x1000b000 0x1000>;
254 gpio-ranges = <&pio 0 0 144>;
256 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt8183-pinctrl.yaml126 When E1=0/E0=0, the strength is 0.125mA.
127 When E1=0/E0=1, the strength is 0.25mA.
128 When E1=1/E0=0, the strength is 0.5mA.
132 0: (E1, E0, EN) = (0, 0, 0)
133 1: (E1, E0, EN) = (0, 0,
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]
H A Dmt6797.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x000>;
38 reg = <0x001>;
45 reg = <0x002>;
52 reg = <0x003>;
59 reg = <0x100>;
66 reg = <0x101>;
73 reg = <0x102>;
80 reg = <0x103>;
[all …]
H A Dmt8516.dtsi21 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
74 clock-frequency = <0>;
80 reg = <0x40000000 0x04000000>;
90 reg = <0x44000000 0x04000000>;
100 reg = <0x4e000000 0x10000>;
110 reg = <0x4f000000 0x20000>;
[all …]
H A Darm-realview-pbx.dtsi44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 reg = <0x40000000 0x04000000>;
105 reg = <0x44000000 0x04000000>;
115 reg = <0x4e000000 0x10000>;
[all …]
H A Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
82 #clock-cells = <0>;
84 clock-frequency = <0>;
89 reg = <0x30000000 0x4000000>;
98 reg = <0x38000000 0x800000>;
113 reg = <0x3c000000 0x4000000>;
121 reg = <0x3a000000 0x10000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]

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