Searched +full:0 +full:x10004000 (Results 1 – 9 of 9) sorted by relevance
27 - cell 0 specifies the bus and device numbers of the root port:30 - cell 1 denotes the upper 32 address bits and should be 045 - 0x81000000: I/O memory region46 - 0x82000000: non-prefetchable memory region47 - 0xc2000000: prefetchable memory region73 - pinctrl-0: phandle for the default/active state of pin configurations.104 - If lanes 0 to 3 are used:150 - Root port 0 uses 4 lanes, root port 1 is unused.158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.171 reg = <0x80003000 0x00000800 /* PADS registers */[all …]
34 pattern: "^switch@[0-9a-f]+$"83 const: 086 "^port@[0-9a-f]+$":111 minimum: 0142 reg = <0 0x401000>,143 <0x10004000 0x7fc000>,144 <0x11010000 0xaf0000>;148 resets = <&reset 0>;152 #size-cells = <0>;154 port0: port@0 {[all …]
28 #size-cells = <0>;39 cpu0: cpu@0 {42 reg = <0x0>;49 reg = <0x1>;81 #clock-cells = <0>;89 reg = <0x6 0x1110000c 0x24>;94 #clock-cells = <0>;100 #clock-cells = <0>;[all...]
43 /* 128 MiB memory @ 0x0 */44 reg = <0x00000000 0x08000000>;48 vmmc: fixedregulator@0 {57 #clock-cells = <0>;63 #clock-cells = <0>;71 #clock-cells = <0>;79 #clock-cells = <0>;87 #clock-cells = <0>;95 #clock-cells = <0>;103 #clock-cells = <0>;[all …]
44 /* 128 MiB memory @ 0x0 */45 reg = <0x00000000 0x08000000>;66 #clock-cells = <0>;72 #clock-cells = <0>;78 #clock-cells = <0>;86 #clock-cells = <0>;94 #clock-cells = <0>;102 #clock-cells = <0>;110 #clock-cells = <0>;118 #clock-cells = <0>;[all …]
45 /* 128 MiB memory @ 0x0 */46 reg = <0x00000000 0x08000000>;67 #clock-cells = <0>;73 #clock-cells = <0>;81 #clock-cells = <0>;89 #clock-cells = <0>;97 #clock-cells = <0>;105 #clock-cells = <0>;113 pclk: pclk@0 {114 #clock-cells = <0>;[all …]
45 * The PB11MPCore has 512 MiB memory @ 0x7000000046 * and the first 256 are also remapped @ 0x0000000048 reg = <0x70000000 0x20000000>;53 #size-cells = <0>;56 MP11_0: cpu@0 {59 reg = <0>;91 reg = <0x1f001000 0x1000>,92 <0x1f000100 0x100>;97 reg = <0x1f002000 0x1000>;99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,[all …]
47 reg = <0x10040000 0x1000>;53 #clock-cells = <0>;59 #size-cells = <0>;62 cpu: cpu@0 {64 reg = <0>;88 reg = <0x10000000 0x20000>;93 reg = <0x10001000 0x100[all...]
20 reg = <0x0 0x00100000 0x0 0xf000>,21 <0x0 0x0010f000 0x0 0x1000>;27 reg = <0x0 0x220000[all...]