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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dti,j721e-pci-host.yaml78 const: 0x104c
82 - 0xb00d
83 - 0xb00f
84 - 0xb010
85 - 0xb012
86 - 0xb013
177 reg = <0x00 0x02900000 0x00 0x1000>,
178 <0x00 0x02907000 0x00 0x400>,
179 <0x00 0x0d000000 0x00 0x00800000>,
180 <0x00 0x10000000 0x00 0x00001000>;
[all …]
H A Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-bcm63xx-hsspi.txt10 - #size-cells: <0>, also as required by generic SPI binding.
22 reg = <0x10001000 0x600>;
32 #size-cells = <0>;
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dingenic,intc.yaml14 pattern: "^interrupt-controller@[0-9a-f]+$"
59 reg = <0x10001000 0x40>;
/freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,mt8192-sys-clock.yaml45 reg = <0x10000000 0x1000>;
52 reg = <0x10001000 0x1000>;
59 reg = <0x10003000 0x1000>;
66 reg = <0x1000c000 0x1000>;
H A Dmediatek,infracfg.txt39 reg = <0 0x10001000 0 0x1000>;
H A Dmediatek,mt8195-sys-clock.yaml53 reg = <0x10000000 0x1000>;
60 reg = <0x10001000 0x1000>;
67 reg = <0x1000c000 0x1000>;
74 reg = <0x11003000 0x1000>;
H A Dmediatek,infracfg.yaml82 reg = <0x10001000 0x1000>;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmediatek,mt8192-sys-clock.yaml45 reg = <0x10000000 0x1000>;
52 reg = <0x10001000 0x1000>;
59 reg = <0x10003000 0x1000>;
66 reg = <0x1000c000 0x1000>;
H A Dmediatek,mt8195-sys-clock.yaml53 reg = <0x10000000 0x1000>;
60 reg = <0x10001000 0x1000>;
67 reg = <0x1000c000 0x1000>;
74 reg = <0x11003000 0x1000>;
H A Dmediatek,infracfg.yaml82 reg = <0x10001000 0x1000>;
/freebsd/crypto/libecc/src/examples/hash/
H A Dtdes.c24 } while( 0 )
34 } while( 0 )
40 0x01010400, 0x00000000, 0x00010000, 0x01010404,
41 0x01010004, 0x00010404, 0x00000004, 0x00010000,
42 0x00000400, 0x01010400, 0x01010404, 0x00000400,
43 0x01000404, 0x01010004, 0x01000000, 0x00000004,
44 0x00000404, 0x01000400, 0x01000400, 0x00010400,
45 0x00010400, 0x01010000, 0x01010000, 0x01000404,
46 0x00010004, 0x01000004, 0x01000004, 0x00010004,
47 0x00000000, 0x00000404, 0x00010404, 0x01000000,
[all …]
/freebsd/crypto/openssl/crypto/des/asm/
H A Ddes-586.pl12 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
25 &asm_init($ARGV[0]);
40 &DES_encrypt("DES_encrypt2",0);
42 &DES_encrypt3("DES_decrypt3",0);
43 &cbc("DES_ncbc_encrypt","DES_encrypt1","DES_encrypt1",0,4,5,3,5,-1);
44 &cbc("DES_ede3_cbc_encrypt","DES_encrypt3","DES_decrypt3",0,6,7,3,4,5);
61 &D_ENCRYPT(0,$L,$R,0,$trans,"eax","ebx","ecx","edx",&swtmp(0));
63 &D_ENCRYPT(1,$R,$L,2,$trans,"eax","ebx","ecx","edx",&swtmp(0));
67 &mov(&swtmp(0),"ecx");
74 for ($i=0; $i<16; $i+=2)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dfsl,imx-dma.yaml64 reg = <0x10001000 0x1000>;
H A Dfsl-imx-dma.txt25 reg = <0x10001000 0x1000>;
/freebsd/sys/dts/arm/
H A Dversatilepb.dts19 reg = <0x10140000 0x1000>;
27 reg = <0x10003000 0x28>;
35 reg = <0x101f1000 0x1000>;
44 reg = <0x101f2000 0x1000>;
53 reg = <0x101f3000 0x1000>;
62 reg = <0x101e2000 0x40>;
70 reg = <0x10000044 0x4
71 0x10001000 0x1000
72 0x41000000 0x01000000
73 0x42000000 0x02000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhip01.dtsi19 #address-cells = <0>;
21 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
26 #clock-cells = <0>;
36 ranges = <0 0x10000000 0x20000000>;
46 reg = <0x10001000 0x1000>;
50 interrupts = <0 32 4>;
56 reg = <0x10002000 0x1000>;
60 interrupts = <0 33 4>;
66 reg = <0x10003000 0x1000>;
70 interrupts = <0 34 4>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Db53.txt57 order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
94 reg = <0x10001000 0x1000>;
105 #size-cells = <0>;
111 #size-cells = <0>;
115 #size-cells = <0>;
117 port0@0 {
118 reg = <0>;
/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dsc9836.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0x0 0x0>;
28 reg = <0x0 0x1>;
35 reg = <0x0 0x2>;
42 reg = <0x0 0x3>;
49 reg = <0 0x10003000 0 0x1000>;
63 reg = <0 0x10001000 0 0x1000>;
77 #size-cells = <0>;
79 port@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8167.dtsi22 reg = <0 0x10000000 0 0x1000>;
28 reg = <0 0x10001000 0 0x1000>;
34 reg = <0 0x10018000 0 0x710>;
40 reg = <0 0x10006000 0 0x1000>;
45 #size-cells = <0>;
53 #power-domain-cells = <0>;
62 #power-domain-cells = <0>;
69 #power-domain-cells = <0>;
78 #size-cells = <0>;
85 #size-cells = <0>;
[all …]
H A Dmt7988a.dtsi15 #size-cells = <0>;
17 cpu@0 {
19 reg = <0x0>;
26 reg = <0x1>;
33 reg = <0x2>;
40 reg = <0x3>;
49 #clock-cells = <0>;
72 reg = <0 0x0c000000 0 0x40000>, /* GICD */
73 <0 0x0c080000 0 0x200000>, /* GICR */
74 <0 0x0c400000 0 0x2000>, /* GICC */
[all …]
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm6362.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
H A Dbcm6328.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
55 #address-cells = <0>;
71 reg = <0x10000004 0x4>;
77 reg = <0x10000010 0x4>;
83 reg = <0x10000020 0x10>,
84 <0x10000030 0x10>;
[all …]

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