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/linux/drivers/gpu/drm/radeon/
H A Drv770.c56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
71 return 0; in rv770_set_uvd_clocks()
75 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
84 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
88 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
90 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
117 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
121 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
122 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmscc,vsc7514-switch.yaml132 reg = <0x1010000 0x10000>,
133 <0x1030000 0x10000>,
134 <0x1080000 0x100>,
135 <0x10e0000 0x10000>,
136 <0x11e0000 0x100>,
137 <0x11f0000 0x100>,
138 <0x1200000 0x100>,
139 <0x1210000 0x100>,
140 <0x1220000 0x100>,
141 <0x1230000 0x100>,
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/mld/tests/
H A Drx.c42 .rx_status_flag = 0,
53 .rx_status_flag = 0,
64 .rx_status_flag = 0,
75 .rx_status_flag = 0,
83 .seq = __cpu_to_le16(0x101),
86 .last_seq = __cpu_to_le16(0x100),
87 .last_sub_frame_idx = 0,
99 .seq = __cpu_to_le16(0x100),
102 .last_seq = __cpu_to_le16(0x100),
103 .last_sub_frame_idx = 0,
[all …]
/linux/drivers/net/ethernet/intel/igbvf/
H A Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
10 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
11 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
12 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
13 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
14 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
15 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
16 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi26 #size-cells = <0>;
28 PowerPC,5121@0 {
30 reg = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
[all …]
/linux/arch/arm64/boot/dts/nuvoton/
H A Dma35d1.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
27 reg = <0x0 0x0>;
35 reg = <0x0 0x1>;
44 cache-size = <0x80000>;
55 reg = <0x0 0x50801000 0 0x1000>, /* GICD */
56 <0x0 0x50802000 0 0x2000>, /* GICC */
57 <0x0 0x50804000 0 0x2000>, /* GICH */
58 <0x0 0x50806000 0 0x2000>; /* GICV */
62 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
[all …]
/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/linux/arch/mips/include/asm/mach-ralink/
H A Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
90 pattern: "^rtu@[0-9a-f]+$"
102 pattern: "^txpru@[0-9a-f]+"
106 pattern: "^pru@[0-9a-f]+$"
119 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
123 ranges = <0x0 0x300000 0x80000>;
125 pruss: pruss@0 {
127 reg = <0x0 0x80000>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5.dtsi40 reg = <0x10000000 0x100>;
45 reg = <0x12250000 0x14>;
53 reg = <0x10440000 0x1000>;
54 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 reg = <0x10481000 0x1000>,
93 <0x10482000 0x2000>,
94 <0x10484000 0x2000>,
95 <0x10486000 0x2000>;
102 reg = <0x10050000 0x5000>;
107 reg = <0x12c00000 0x100>;
[all …]
H A Dexynos4.dtsi68 reg = <0x03810000 0x0c>;
79 reg = <0x03830000 0x100>;
88 samsung,idma-addr = <0x03000000>;
95 reg = <0x10000000 0x100>;
100 reg = <0x10500000 0x2000>;
105 reg = <0x12570000 0x14>;
110 reg = <0x10023c40 0x20>;
111 #power-domain-cells = <0>;
117 reg = <0x10023c60 0x20>;
118 #power-domain-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi23 service_reserved: svcbuffer@0 {
25 reg = <0x0 0x80000000 0x0 0x2000000>;
26 alignment = <0x1000>;
33 #size-cells = <0>;
35 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x100>;
51 reg = <0x200>;
58 reg = <0x300>;
71 reg = <0x0 0x1d000000 0 0x10000>,
[all …]
H A Dsocfpga_agilex.dtsi22 service_reserved: svcbuffer@0 {
24 reg = <0x0 0x0 0x0 0x2000000>;
25 alignment = <0x1000>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
38 reg = <0x0>;
45 reg = <0x1>;
52 reg = <0x2>;
59 reg = <0x3>;
77 #address-cells = <0x2>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_11_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_11_2_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_10_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
43 reg = <0x0 0x43000000 0x0 0x20000>;
46 ranges = <0x0 0x0 0x43000000 0x20000>;
51 reg = <0x00000014 0x4>;
[all …]
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
/linux/sound/pci/oxygen/
H A Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
38 reg = <0x0>;
46 reg = <0x1>;
54 reg = <0x2>;
62 reg = <0x3>;
86 #address-cells = <0x2>;
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A Digb_ethtool.c112 TEST_REG = 0,
129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)
147 0 : rd32(E1000_STATUS); in igb_get_link_ksettings()
240 /* MDI-X => 2; MDI =>1; Invalid =>0 */ in igb_get_link_ksettings()
257 return 0; in igb_get_link_ksettings()
338 /* fix up the value for auto (3 => 0) as zero is mapped in igb_set_link_ksettings()
355 return 0; in igb_set_link_ksettings()
399 int retval = 0; in igb_set_pauseparam()
435 for (i = 0; i < adapter->num_rx_queues; i++) { in igb_set_pauseparam()
472 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); in igb_get_regs()
[all …]
/linux/drivers/of/unittest-data/
H A Dtests-address.dtsi17 ranges = <0x70000000 0x70000000 0x50000000>,
18 <0x00000000 0xd0000000 0x20000000>;
19 dma-ranges = <0x0 0x20000000 0x40000000>;
22 reg = <0x70000000 0x1000>;
28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
32 reg = <0x0 0x1000 0x0 0x1000>;
40 reg = <0x90000000 0x1000>;
41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;
42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,
[all …]
/linux/include/linux/mfd/syscon/
H A Datmel-matrix.h11 #define AT91SAM9260_MATRIX_MCFG 0x00
12 #define AT91SAM9260_MATRIX_SCFG 0x40
13 #define AT91SAM9260_MATRIX_PRS 0x80
14 #define AT91SAM9260_MATRIX_MRCR 0x100
15 #define AT91SAM9260_MATRIX_EBICSA 0x11c
17 #define AT91SAM9261_MATRIX_MRCR 0x0
18 #define AT91SAM9261_MATRIX_SCFG 0x4
19 #define AT91SAM9261_MATRIX_TCR 0x24
20 #define AT91SAM9261_MATRIX_EBICSA 0x30
21 #define AT91SAM9261_MATRIX_USBPUCR 0x34
[all …]
/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-video.c24 u32 value = 0; in medusa_enable_bluefield_output()
25 u32 tmp = 0; in medusa_enable_bluefield_output()
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
[all …]

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