Searched +full:0 +full:x0fffc000 (Results 1 – 5 of 5) sorted by relevance
21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)35 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]41 * IO 0x00200000+0x100000 -> 0xf4000000+0x10000043 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x10000044 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x10000045 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x00400047 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x10000048 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x10000049 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x10000051 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000[all …]
45 reg = <0x0fffc000 0x4000>;
48 #size-cells = <0>;49 cpu@0 {52 reg = <0x0>;60 reg = <0x0fffc000 0x4000>;66 #clock-cells = <0>;72 #clock-cells = <0>;78 #clock-cells = <0>;79 clock-frequency = <0>;84 #clock-cells = <0>;89 usbphy0: usbphy-0 {[all …]
51 #size-cells = <0>;52 cpu0: cpu@0 {55 reg = <0x0>;84 reg = <0x0fffc000 0x4000>;90 #clock-cells = <0>;96 #clock-cells = <0>;102 #clock-cells = <0>;103 clock-frequency = <0>;108 #clock-cells = <0>;119 usbphy0: usbphy-0 {[all …]
22 #define AR_CR 0x000823 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)24 #define AR_CR_RXD 0x0000002025 #define AR_CR_SWI 0x0000004027 #define AR_RXDP 0x000C29 #define AR_CFG 0x001430 #define AR_CFG_SWTD 0x0000000131 #define AR_CFG_SWTB 0x0000000232 #define AR_CFG_SWRD 0x0000000433 #define AR_CFG_SWRB 0x00000008[all …]