| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am642-evm-pcie0-ep.dtso | 34 reg = <0x00 0x0f102000 0x00 0x1000>,
35 <0x00 0x0f100000 0x00 0x400>,
36 <0x00 0x0d000000 0x00 0x00800000>,
37 <0x00 0x68000000 0x00 0x08000000>;
44 clocks = <&k3_clks 114 0>;
49 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
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| H A D | k3-j722s-main.dtsi | 12 serdes_refclk: clk-0 {
14 #clock-cells = <0>;
15 clock-frequency = <0>;
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
39 reg = <0x0f000000 0x00010000>;
41 resets = <&serdes_wiz0 0>;
53 #size-cells = <0>;
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
[all …]
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| H A D | k3-am64-main.dtsi | 13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
43 reg = <0x0 0x43000000 0x0 0x20000>;
46 ranges = <0x0 0x0 0x43000000 0x20000>;
51 reg = <0x00000014 0x4>;
[all …]
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | qcom,qcs8300-tlmm.yaml | 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
105 reg = <0x0f100000 0x300000>;
109 gpio-ranges = <&tlmm 0 0 134>;
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| H A D | qcom,sm8250-pinctrl.yaml | 63 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
109 reg = <0x0f100000 0x300000>,
110 <0x0f500000 0x300000>,
111 <0x0f900000 0x300000>;
118 gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */
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| H A D | qcom,sdx75-tlmm.yaml | 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
104 reg = <0x0f100000 0x300000>;
107 gpio-ranges = <&tlmm 0 0 133>;
|
| H A D | qcom,sdx55-pinctrl.yaml | 53 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
106 reg = <0x0f100000 0x300000>;
109 gpio-ranges = <&tlmm 0 0 108>;
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| H A D | qcom,sm8750-tlmm.yaml | 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$"
111 reg = <0x0f100000 0x300000>;
114 gpio-ranges = <&tlmm 0 0 216>;
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| H A D | qcom,sm8650-tlmm.yaml | 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
114 reg = <0x0f100000 0x300000>;
117 gpio-ranges = <&tlmm 0 0 211>;
|
| H A D | qcom,sm8450-tlmm.yaml | 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
107 reg = <0x0f100000 0x300000>;
110 gpio-ranges = <&tlmm 0 0 211>;
|
| H A D | qcom,sm8350-tlmm.yaml | 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$"
108 reg = <0x0f100000 0x300000>;
114 gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */
|
| H A D | qcom,sm8550-tlmm.yaml | 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
121 reg = <0x0f100000 0x300000>;
124 gpio-ranges = <&tlmm 0 0 211>;
|
| H A D | qcom,sar2130p-tlmm.yaml | 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
111 reg = <0x0f100000 0x300000>;
114 gpio-ranges = <&tlmm 0 0 156>;
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| H A D | qcom,sc8280xp-tlmm.yaml | 55 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
110 reg = <0x0f100000 0x300000>;
116 gpio-ranges = <&tlmm 0 0 230>;
|
| H A D | qcom,x1e80100-tlmm.yaml | 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$"
110 reg = <0x0f100000 0xf00000>;
113 gpio-ranges = <&tlmm 0 0 239>;
|
| H A D | qcom,sm6350-tlmm.yaml | 61 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
112 reg = <0x0f100000 0x300000>;
127 gpio-ranges = <&tlmm 0 0 157>;
|
| /linux/arch/arm64/boot/dts/apple/ |
| H A D | s800-0-3.dtsi | 22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled in by loader */
40 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled in by loader */
53 i-cache-size = <0x10000>;
[all …]
|
| H A D | s8001.dtsi | 22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled in by loader */
40 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled in by loader */
53 i-cache-size = <0x10000>;
[all …]
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| H A D | t8011.dtsi | 22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled by loader */
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled by loader */
53 i-cache-size = <0x10000>; /* P-core */
[all …]
|
| H A D | t8010.dtsi | 22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled by loader */
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled by loader */
53 i-cache-size = <0x10000>; /* P-core */
[all …]
|
| H A D | t8012.dtsi | 22 #clock-cells = <0>;
29 #size-cells = <0>;
33 reg = <0x0 0x10000>;
34 cpu-release-addr = <0 0>; /* To be filled by loader */
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
46 reg = <0x0 0x10001>;
47 cpu-release-addr = <0 0>; /* To be filled by loader */
53 i-cache-size = <0x10000>; /* P-core */
54 d-cache-size = <0x10000>; /* P-core */
[all …]
|
| /linux/arch/arm/boot/dts/qcom/ |
| H A D | qcom-msm8226-samsung-matisse-common.dtsi | 35 reg = <0x03200000 0x800000>;
88 pinctrl-0 = <&backlight_i2c_default_state>;
94 #size-cells = <0>;
98 reg = <0x2c>;
100 dev-ctrl = /bits/ 8 <0x80>;
101 init-brt = /bits/ 8 <0x3f>;
103 pwms = <&backlight_pwm 0 100000>;
107 rom-addr = /bits/ 8 <0xa0>;
108 rom-val = /bits/ 8 <0x44>;
112 rom-addr = /bits/ 8 <0xa1>;
[all …]
|
| H A D | qcom-apq8026-samsung-milletwifi.dts | 39 reg = <0x03200000 0x800000>;
92 pinctrl-0 = <&backlight_i2c_default_state>;
98 #size-cells = <0>;
102 reg = <0x2c>;
105 dev-ctrl = /bits/ 8 <0x80>;
106 init-brt = /bits/ 8 <0x3f>;
114 rom-addr = /bits/ 8 <0xa3>;
115 rom-val = /bits/ 8 <0x5e>;
120 * (0, 120deg, 240deg, -, -, -),
124 rom-addr = /bits/ 8 <0xa5>;
[all …]
|
| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | sm4450.dtsi | 29 #clock-cells = <0>;
35 #clock-cells = <0>;
39 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
[all …]
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| H A D | sm8750.dtsi | 28 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
49 reg = <0x0 0x100>;
59 reg = <0x0 0x200>;
69 reg = <0x0 0x300>;
79 reg = <0x0 0x400>;
89 reg = <0x0 0x500>;
99 reg = <0x0 0x10000>;
115 reg = <0x0 0x10100>;
[all …]
|