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/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8723x.h28 IQK_ROUND_INVALID = 0xff,
45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 res4[48]; /* 0xd0 */
54 u8 vendor_id[2]; /* 0x100 */
55 u8 product_id[2]; /* 0x102 */
56 u8 usb_option; /* 0x104 */
57 u8 res5[2]; /* 0x105 */
58 u8 mac_addr[ETH_ALEN]; /* 0x107 */
62 u8 res4[0x4a]; /* 0xd0 */
63 u8 mac_addr[ETH_ALEN]; /* 0x11a */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/include/video/
H A Dradeon.h6 #define RADEON_REGSIZE 0x4000
9 #define MM_INDEX 0x0000
10 #define MM_DATA 0x0004
11 #define BUS_CNTL 0x0030
12 #define HI_STAT 0x004C
13 #define BUS_CNTL1 0x0034
14 #define I2C_CNTL_1 0x0094
15 #define CNFG_CNTL 0x00E0
16 #define CNFG_MEMSIZE 0x00F8
17 #define CNFG_APER_0_BASE 0x0100
[all …]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/sound/soc/codecs/
H A Dlpass-rx-macro.c21 #define CDC_RX_TOP_TOP_CFG0 (0x0000)
22 #define CDC_RX_TOP_SWR_CTRL (0x0008)
23 #define CDC_RX_TOP_DEBUG (0x000C)
24 #define CDC_RX_TOP_DEBUG_BUS (0x0010)
25 #define CDC_RX_TOP_DEBUG_EN0 (0x0014)
26 #define CDC_RX_TOP_DEBUG_EN1 (0x0018)
27 #define CDC_RX_TOP_DEBUG_EN2 (0x001C)
28 #define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020)
29 #define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024)
30 #define CDC_RX_TOP_HPHL_COMP_LUT (0x0028)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]
H A Ddcn_3_0_3_offset.h12 // base address: 0x0
13 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
14 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
15 …VGA_MEM_READ_PAGE_ADDR 0x0001
16 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
17 …VGA_RENDER_CONTROL 0x0000
19 …VGA_SEQUENCER_RESET_CONTROL 0x0001
21 …VGA_MODE_CONTROL 0x0002
23 …VGA_SURFACE_PITCH_SELECT 0x0003
25 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_0_1_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_4_1_0_offset.h11 // base address: 0x0
12 …DENTIST_DISPCLK_CNTL 0x0064
17 // base address: 0x0
18 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
20 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
22 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
24 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
26 …DP_DTO_DBUF_EN 0x0044
28 …DSCCLK3_DTO_PARAM 0x0045
30 …DSCCLK4_DTO_PARAM 0x0046
[all …]
H A Ddcn_3_0_2_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_3_1_6_offset.h30 // base address: 0x1300000
31 …CONTROLLER0_GLOBAL_CAPABILITIES 0x4b7000
33 …CONTROLLER0_MINOR_VERSION 0x4b7000
35 …CONTROLLER0_MAJOR_VERSION 0x4b7000
37 …CONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b7001
39 …CONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b7001
41 …CONTROLLER0_GLOBAL_CONTROL 0x4b7002
43 …CONTROLLER0_WAKE_ENABLE 0x4b7003
45 …CONTROLLER0_STATE_CHANGE_STATUS 0x4b7003
47 …CONTROLLER0_GLOBAL_STATUS 0x4b7004
[all …]
H A Ddcn_3_1_4_offset.h31 // base address: 0x0
32 …AZCONTROLLER0_CORB_WRITE_POINTER 0x0000
33 …e regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 0
34 …AZCONTROLLER0_CORB_READ_POINTER 0x0000
35 …e regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 0
36 …AZCONTROLLER0_CORB_CONTROL 0x0001
37 …e regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 0
38 …AZCONTROLLER0_CORB_STATUS 0x0001
39 …e regAZCONTROLLER0_CORB_STATUS_BASE_IDX 0
40 …AZCONTROLLER0_CORB_SIZE 0x0001
[all …]
H A Ddcn_3_1_5_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
46 …DCCG_GATE_DISABLE_CNTL4 0x0049
[all …]
H A Ddcn_3_1_2_offset.h27 // base address: 0x1300000
28 …CONTROLLER0_GLOBAL_CAPABILITIES 0x4b7000
30 …CONTROLLER0_MINOR_VERSION 0x4b7000
32 …CONTROLLER0_MAJOR_VERSION 0x4b7000
34 …CONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b7001
36 …CONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b7001
38 …CONTROLLER0_GLOBAL_CONTROL 0x4b7002
40 …CONTROLLER0_WAKE_ENABLE 0x4b7003
42 …CONTROLLER0_STATE_CHANGE_STATUS 0x4b7003
44 …CONTROLLER0_GLOBAL_STATUS 0x4b7004
[all …]
H A Ddcn_3_0_0_offset.h8 // base address: 0x0
9 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
10 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
11 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
12 …VGA_MEM_READ_PAGE_ADDR 0x0001
13 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
14 …VGA_RENDER_CONTROL 0x0000
16 …VGA_SEQUENCER_RESET_CONTROL 0x0001
18 …VGA_MODE_CONTROL 0x0002
20 …VGA_SURFACE_PITCH_SELECT 0x0003
[all …]
H A Ddcn_2_0_0_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
/linux/fs/hfsplus/
H A Dtables.c24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h27 // base address: 0x48
28 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
29 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
33 // base address: 0x4c
34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
35 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
39 // base address: 0x0
40 …DC_PERFMON0_PERFCOUNTER_CNTL 0x0020
42 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
44 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022
[all …]