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/linux/Documentation/devicetree/bindings/mtd/
H A Dflctl-nand.txt26 reg = <0xe6a30000 0x100>;
27 interrupts = <0x0d80>;
35 system@0 {
37 reg = <0x0 0x8000000>;
42 reg = <0x8000000 0x10000000>;
47 reg = <0x18000000 0x8000000>;
/linux/lib/crc/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/linux/arch/arm/mach-imx/
H A Dtzic.c28 #define TZIC_INTCNTL 0x0000 /* Control register */
29 #define TZIC_INTTYPE 0x0004 /* Controller Type register */
30 #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
31 #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
32 #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
33 #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
34 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
35 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
36 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
37 #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
[all …]
/linux/drivers/irqchip/
H A Dirq-davinci-cp-intc.c22 #define DAVINCI_CP_INTC_CTRL 0x04
23 #define DAVINCI_CP_INTC_HOST_CTRL 0x0c
24 #define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10
25 #define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24
26 #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28
27 #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2c
28 #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34
29 #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38
30 #define DAVINCI_CP_INTC_PRIO_IDX 0x80
31 #define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
[all …]
H A Dirq-pruss-intc.c34 #define PRU_INTC_REVID 0x0000
35 #define PRU_INTC_CR 0x0004
36 #define PRU_INTC_GER 0x0010
37 #define PRU_INTC_GNLR 0x001c
38 #define PRU_INTC_SISR 0x0020
39 #define PRU_INTC_SICR 0x0024
40 #define PRU_INTC_EISR 0x0028
41 #define PRU_INTC_EICR 0x002c
42 #define PRU_INTC_HIEISR 0x0034
43 #define PRU_INTC_HIDISR 0x0038
[all …]
/linux/drivers/media/dvb-frontends/
H A Ddib0070.c25 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
31 } while (0)
33 #define DIB0070_P1D 0x00
34 #define DIB0070_P1F 0x01
35 #define DIB0070_P1G 0x03
36 #define DIB0070S_P1A 0x02
73 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0070_read_reg()
75 return 0; in dib0070_read_reg()
78 state->i2c_write_buffer[0] = reg; in dib0070_read_reg()
80 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib0070_read_reg()
[all …]
H A Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]
/linux/drivers/media/pci/smipcie/
H A Dsmipcie.h31 #define MSI_CONTROL_REG_BASE 0x0800
32 #define SYSTEM_CONTROL_REG_BASE 0x0880
33 #define PCIE_EP_DEBUG_REG_BASE 0x08C0
34 #define IR_CONTROL_REG_BASE 0x0900
35 #define I2C_A_CONTROL_REG_BASE 0x0940
36 #define I2C_B_CONTROL_REG_BASE 0x0980
37 #define ATV_PORTA_CONTROL_REG_BASE 0x09C0
38 #define DTV_PORTA_CONTROL_REG_BASE 0x0A00
39 #define AES_PORTA_CONTROL_REG_BASE 0x0A80
40 #define DMA_PORTA_CONTROL_REG_BASE 0x0AC0
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h13 #define SXGBE_CORE_TX_CONFIG_REG 0x0000
14 #define SXGBE_CORE_RX_CONFIG_REG 0x0004
15 #define SXGBE_CORE_PKT_FILTER_REG 0x0008
16 #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
17 #define SXGBE_CORE_HASH_TABLE_REG0 0x0010
18 #define SXGBE_CORE_HASH_TABLE_REG1 0x0014
19 #define SXGBE_CORE_HASH_TABLE_REG2 0x0018
20 #define SXGBE_CORE_HASH_TABLE_REG3 0x001C
21 #define SXGBE_CORE_HASH_TABLE_REG4 0x0020
22 #define SXGBE_CORE_HASH_TABLE_REG5 0x0024
[all …]
/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h19 #define SMIAPP_REG_U16_MODEL_ID CCI_REG16(0x0000)
20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
25 #define SMIAPP_REG_U16_DATA_PEDESTAL CCI_REG16(0x0008)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
[all …]
/linux/drivers/media/pci/ngene/
H A Dngene.h32 #define NGENE_VID 0x18c3
33 #define NGENE_PID 0x0720
43 #define DEMOD_TYPE_STV090X 0
48 #define DEMOD_TYPE_STV0910 (DEMOD_TYPE_XO2 + 0)
55 #define NGENE_XO2_TYPE_NONE 0
60 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
69 SMODE_AUDIO_SPDIF = 0x20,
70 SMODE_AVSYNC = 0x10,
71 SMODE_TRANSPORT_STREAM = 0x08,
72 SMODE_AUDIO_CAPTURE = 0x04,
[all …]
/linux/drivers/media/pci/cx88/
H A Dcx88-tvaudio.c52 "Radio deemphasis time constant, 0=None, 1=50us (elsewhere), 2=75us (USA)");
58 } while (0)
96 for (i = 0; l[i].reg; i++) { in set_audio_registers()
120 cx_write(AUD_INIT_LD, 0x0001); in set_audio_start()
121 cx_write(AUD_SOFT_RESET, 0x0001); in set_audio_start()
130 cx_write(AUD_RATE_THRES_DMD, 0x000000C0); in set_audio_finish()
142 cx_write(AUD_I2SCNTL, 0); in set_audio_finish()
143 /* cx_write(AUD_APB_IN_RATE_ADJ, 0); */ in set_audio_finish()
151 cx_write(AUD_SOFT_RESET, 0x0000); in set_audio_finish()
166 {AUD_AFE_12DB_EN, 0x00000001}, in set_audio_standard_BTSC()
[all …]
/linux/drivers/crypto/inside-secure/
H A Dsafexcel.h20 #define EIP197_HIA_VERSION_BE 0xca35
21 #define EIP197_HIA_VERSION_LE 0x35ca
22 #define EIP97_VERSION_LE 0x9e61
23 #define EIP196_VERSION_LE 0x3bc4
24 #define EIP197_VERSION_LE 0x3ac5
25 #define EIP96_VERSION_LE 0x9f60
26 #define EIP201_VERSION_LE 0x36c9
27 #define EIP206_VERSION_LE 0x31ce
28 #define EIP207_VERSION_LE 0x30cf
29 #define EIP197_REG_LO16(reg) (reg & 0xffff)
[all …]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-common.h12 #define DMA_MR 0x3000
13 #define DMA_SBMR 0x3004
14 #define DMA_ISR 0x3008
15 #define DMA_AXIARCR 0x3010
16 #define DMA_AXIAWCR 0x3018
17 #define DMA_AXIAWARCR 0x301c
18 #define DMA_DSR0 0x3020
19 #define DMA_DSR1 0x3024
20 #define DMA_TXEDMACR 0x3040
21 #define DMA_RXEDMACR 0x3044
[all …]
/linux/include/video/
H A Dradeon.h6 #define RADEON_REGSIZE 0x4000
9 #define MM_INDEX 0x0000
10 #define MM_DATA 0x0004
11 #define BUS_CNTL 0x0030
12 #define HI_STAT 0x004C
13 #define BUS_CNTL1 0x0034
14 #define I2C_CNTL_1 0x0094
15 #define CNFG_CNTL 0x00E0
16 #define CNFG_MEMSIZE 0x00F8
17 #define CNFG_APER_0_BASE 0x0100
[all …]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dradio.c30 0x0002, 0x0003, 0x0001, 0x000F,
31 0x0006, 0x0007, 0x0005, 0x000F,
32 0x000A, 0x000B, 0x0009, 0x000F,
33 0x000E, 0x000F, 0x000D, 0x000F,
41 u16 flipped = 0x0000; in flip_4bit()
43 B43legacy_BUG_ON(!((value & ~0x000F) == 0x0000)); in flip_4bit()
45 flipped |= (value & 0x0001) << 3; in flip_4bit()
46 flipped |= (value & 0x0002) << 1; in flip_4bit()
47 flipped |= (value & 0x0004) >> 1; in flip_4bit()
48 flipped |= (value & 0x0008) >> 3; in flip_4bit()
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h107 #define CLEAR_FLAG_SFT 0
108 #define CLEAR_FLAG_MASK_SFT BIT(0)
153 #define AUDIO_AFE_ON_SFT 0
154 #define AUDIO_AFE_ON_MASK_SFT BIT(0)
157 #define AFE_ON_RETM_SFT 0
158 #define AFE_ON_RETM_MASK_SFT BIT(0)
187 #define I2S_EN_SFT 0
188 #define I2S_EN_MASK_SFT BIT(0)
209 #define I2S2_EN_SFT 0
210 #define I2S2_EN_MASK_SFT BIT(0)
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-reg.h26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
34 #define MOD_DAI_ON_MASK 0x1
35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30)
37 #define DAI_ON_MASK 0x1
38 #define DAI_ON_MASK_SFT (0x1 << 29)
40 #define DAI2_ON_MASK 0x1
41 #define DAI2_ON_MASK_SFT (0x1 << 28)
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_g.c75 {.att = 3,.with_padmix = 0,}, in generate_rfatt_list()
76 {.att = 1,.with_padmix = 0,}, in generate_rfatt_list()
77 {.att = 5,.with_padmix = 0,}, in generate_rfatt_list()
78 {.att = 7,.with_padmix = 0,}, in generate_rfatt_list()
79 {.att = 9,.with_padmix = 0,}, in generate_rfatt_list()
80 {.att = 2,.with_padmix = 0,}, in generate_rfatt_list()
81 {.att = 0,.with_padmix = 0,}, in generate_rfatt_list()
82 {.att = 4,.with_padmix = 0,}, in generate_rfatt_list()
83 {.att = 6,.with_padmix = 0,}, in generate_rfatt_list()
84 {.att = 8,.with_padmix = 0,}, in generate_rfatt_list()
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-apq8084.c39 .l_reg = 0x0004,
40 .m_reg = 0x0008,
41 .n_reg = 0x000c,
42 .config_reg = 0x0014,
43 .mode_reg = 0x0000,
44 .status_reg = 0x001c,
57 .enable_reg = 0x1480,
58 .enable_mask = BIT(0),
70 .l_reg = 0x0044,
71 .m_reg = 0x0048,
[all …]
/linux/sound/soc/codecs/
H A Dlpass-rx-macro.c21 #define CDC_RX_TOP_TOP_CFG0 (0x0000)
22 #define CDC_RX_TOP_SWR_CTRL (0x0008)
23 #define CDC_RX_TOP_DEBUG (0x000C)
24 #define CDC_RX_TOP_DEBUG_BUS (0x0010)
25 #define CDC_RX_TOP_DEBUG_EN0 (0x0014)
26 #define CDC_RX_TOP_DEBUG_EN1 (0x0018)
27 #define CDC_RX_TOP_DEBUG_EN2 (0x001C)
28 #define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020)
29 #define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024)
30 #define CDC_RX_TOP_HPHL_COMP_LUT (0x0028)
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_reg.h62 #define RADEON_MC_AGP_LOCATION 0x014c
63 #define RADEON_MC_AGP_START_MASK 0x0000FFFF
64 #define RADEON_MC_AGP_START_SHIFT 0
65 #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
67 #define RADEON_MC_FB_LOCATION 0x0148
68 #define RADEON_MC_FB_START_MASK 0x0000FFFF
69 #define RADEON_MC_FB_START_SHIFT 0
70 #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
72 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
73 #define RADEON_AGP_BASE 0x0170
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]

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