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12

/linux/drivers/staging/media/meson/vdec/
H A Ddos_regs.h11 #define VDEC_ASSIST_AMR1_INT8 0x00b4
13 #define ASSIST_MBOX1_CLR_REG 0x01d4
14 #define ASSIST_MBOX1_MASK 0x01d8
16 #define MPSR 0x0c04
17 #define MCPU_INTR_MSK 0x0c10
18 #define CPSR 0x0c84
20 #define IMEM_DMA_CTRL 0x0d00
21 #define IMEM_DMA_ADR 0x0d04
22 #define IMEM_DMA_COUNT 0x0d08
23 #define LMEM_DMA_CTRL 0x0d40
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_pcie2.h5 #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
6 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
7 #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
8 #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
9 #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
11 #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
12 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
13 #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
14 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
[all …]
H A Dbcma_driver_chipcommon.h10 #define BCMA_CC_ID 0x0000
11 #define BCMA_CC_ID_ID 0x0000FFFF
12 #define BCMA_CC_ID_ID_SHIFT 0
13 #define BCMA_CC_ID_REV 0x000F0000
15 #define BCMA_CC_ID_PKG 0x00F00000
17 #define BCMA_CC_ID_NRCORES 0x0F000000
19 #define BCMA_CC_ID_TYPE 0xF0000000
21 #define BCMA_CC_CAP 0x0004 /* Capabilities */
22 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
[all …]
/linux/drivers/media/platform/ti/vpe/
H A Dcsc.c51 0x0400, 0x0000, 0x057D, 0x0400, 0x1EA7, 0x1D35,
52 0x0400, 0x06EF, 0x1FFE, 0x0D40, 0x0210, 0x0C88,
57 0x04A8, 0x1FFE, 0x0662, 0x04A8, 0x1E6F, 0x1CBF,
58 0x04A8, 0x0812, 0x1FFF, 0x0C84, 0x0220, 0x0BAC,
65 0x0400, 0x0000, 0x0629, 0x0400, 0x1F45, 0x1E2B,
66 0x0400, 0x0742, 0x0000, 0x0CEC, 0x0148, 0x0C60,
71 0x04A8, 0x0000, 0x072C, 0x04A8, 0x1F26, 0x1DDE,
72 0x04A8, 0x0873, 0x0000, 0x0C20, 0x0134, 0x0B7C,
81 0x0132, 0x0259, 0x0075, 0x1F50, 0x1EA5, 0x020B,
82 0x020B, 0x1E4A, 0x1FAB, 0x0000, 0x0200, 0x0200,
[all …]
/linux/drivers/video/fbdev/
H A Dclps711x-fb.c26 #define CLPS711X_LCDCON (0x0000)
29 #define CLPS711X_PALLSW (0x0280)
30 #define CLPS711X_PALMSW (0x02c0)
31 #define CLPS711X_FBADDR (0x0d40)
54 mask = 0xf << shift; in clps711x_fb_setcolreg()
58 level = 0xf - level; in clps711x_fb_setcolreg()
64 return 0; in clps711x_fb_setcolreg()
80 if (val < 0x01 || val > 0x3f) in clps711x_fb_check_var()
85 if (val < 0x001 || val > 0x1fff) in clps711x_fb_check_var()
88 var->transp.msb_right = 0; in clps711x_fb_check_var()
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8723x.h28 IQK_ROUND_INVALID = 0xff,
45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 res4[48]; /* 0xd0 */
54 u8 vendor_id[2]; /* 0x100 */
55 u8 product_id[2]; /* 0x102 */
56 u8 usb_option; /* 0x104 */
57 u8 res5[2]; /* 0x105 */
58 u8 mac_addr[ETH_ALEN]; /* 0x107 */
62 u8 res4[0x4a]; /* 0xd0 */
63 u8 mac_addr[ETH_ALEN]; /* 0x11a */
[all …]
H A Dreg.h8 #define REG_SYS_FUNC_EN 0x0002
15 #define BIT_FEN_BB_RSTB BIT(0)
18 #define REG_SYS_PW_CTRL 0x0004
21 #define REG_APS_FSMCO 0x0004
25 #define REG_SYS_CLK_CTRL 0x0008
28 #define REG_SYS_CLKR 0x0008
33 #define REG_RSV_CTRL 0x001C
34 #define DISABLE_PI 0x3
35 #define ENABLE_PI 0x2
37 #define BIT_WLMCU_IOIF BIT(0)
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h13 #define SXGBE_CORE_TX_CONFIG_REG 0x0000
14 #define SXGBE_CORE_RX_CONFIG_REG 0x0004
15 #define SXGBE_CORE_PKT_FILTER_REG 0x0008
16 #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
17 #define SXGBE_CORE_HASH_TABLE_REG0 0x0010
18 #define SXGBE_CORE_HASH_TABLE_REG1 0x0014
19 #define SXGBE_CORE_HASH_TABLE_REG2 0x0018
20 #define SXGBE_CORE_HASH_TABLE_REG3 0x001C
21 #define SXGBE_CORE_HASH_TABLE_REG4 0x0020
22 #define SXGBE_CORE_HASH_TABLE_REG5 0x0024
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3xxx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
18 reg = <0x0d40>;
22 #clock-cells = <0>;
27 reg = <0x1270>;
32 #clock-cells = <0>;
35 reg = <0x0d70>;
40 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_d.h26 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE
27 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE
28 #define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE
29 #define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE
30 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE
31 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE
32 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E
33 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E
34 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E
35 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E
[all …]
/linux/sound/hda/codecs/realtek/
H A Drealtek.c15 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in __alc_read_coefex_idx()
16 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PROC_COEF, 0); in __alc_read_coefex_idx()
31 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in __alc_write_coefex_idx()
32 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PROC_COEF, coef_val); in __alc_write_coefex_idx()
63 /* a special bypass for COEF 0; read the cached value at the second time */
69 spec->coef0 = alc_read_coef_idx(codec, 0); in alc_get_coef0()
106 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, in alc_write_gpio_data()
133 snd_hda_codec_write(codec, codec->core.afg, 0, in alc_write_gpio()
135 snd_hda_codec_write(codec, codec->core.afg, 0, in alc_write_gpio()
153 alc_fixup_gpio(codec, action, 0x01); in alc_fixup_gpio1()
[all …]
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-reg.h15 #define AUDIO_TOP_CON0 (0x0000)
16 #define AUDIO_TOP_CON1 (0x0004)
17 #define AUDIO_TOP_CON2 (0x0008)
18 #define AUDIO_TOP_CON3 (0x000c)
20 #define AFE_DAC_CON0 (0x0010)
21 #define AFE_DAC_CON1 (0x0014)
22 #define AFE_I2S_CON (0x0018)
23 #define AFE_CONN0 (0x0020)
24 #define AFE_CONN1 (0x0024)
25 #define AFE_CONN2 (0x0028)
[all …]
/linux/include/video/
H A Dradeon.h6 #define RADEON_REGSIZE 0x4000
9 #define MM_INDEX 0x0000
10 #define MM_DATA 0x0004
11 #define BUS_CNTL 0x0030
12 #define HI_STAT 0x004C
13 #define BUS_CNTL1 0x0034
14 #define I2C_CNTL_1 0x0094
15 #define CNFG_CNTL 0x00E0
16 #define CNFG_MEMSIZE 0x00F8
17 #define CNFG_APER_0_BASE 0x0100
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h26 // base address: 0x0
27 … 0x0000 // duplicate
28 … 0x0002 // duplicate
29 … 0x0004 // duplicate
30 … 0x0006 // duplicate
31 … 0x0008 // duplicate
32 … 0x0009 // duplicate
33 … 0x000a // duplicate
34 … 0x000b // duplicate
35 … 0x000c // duplicate
[all …]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h107 #define CLEAR_FLAG_SFT 0
108 #define CLEAR_FLAG_MASK_SFT BIT(0)
153 #define AUDIO_AFE_ON_SFT 0
154 #define AUDIO_AFE_ON_MASK_SFT BIT(0)
157 #define AFE_ON_RETM_SFT 0
158 #define AFE_ON_RETM_MASK_SFT BIT(0)
187 #define I2S_EN_SFT 0
188 #define I2S_EN_MASK_SFT BIT(0)
209 #define I2S2_EN_SFT 0
210 #define I2S2_EN_MASK_SFT BIT(0)
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-reg.h26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
34 #define MOD_DAI_ON_MASK 0x1
35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30)
37 #define DAI_ON_MASK 0x1
38 #define DAI_ON_MASK_SFT (0x1 << 29)
40 #define DAI2_ON_MASK 0x1
41 #define DAI2_ON_MASK_SFT (0x1 << 28)
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-apq8084.c39 .l_reg = 0x0004,
40 .m_reg = 0x0008,
41 .n_reg = 0x000c,
42 .config_reg = 0x0014,
43 .mode_reg = 0x0000,
44 .status_reg = 0x001c,
57 .enable_reg = 0x1480,
58 .enable_mask = BIT(0),
70 .l_reg = 0x0044,
71 .m_reg = 0x0048,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_7_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
/linux/sound/soc/codecs/
H A Dlpass-rx-macro.c21 #define CDC_RX_TOP_TOP_CFG0 (0x0000)
22 #define CDC_RX_TOP_SWR_CTRL (0x0008)
23 #define CDC_RX_TOP_DEBUG (0x000C)
24 #define CDC_RX_TOP_DEBUG_BUS (0x0010)
25 #define CDC_RX_TOP_DEBUG_EN0 (0x0014)
26 #define CDC_RX_TOP_DEBUG_EN1 (0x0018)
27 #define CDC_RX_TOP_DEBUG_EN2 (0x001C)
28 #define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020)
29 #define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024)
30 #define CDC_RX_TOP_HPHL_COMP_LUT (0x0028)
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dsky2.h12 PCI_DEV_REG1 = 0x40,
13 PCI_DEV_REG2 = 0x44,
14 PCI_DEV_STATUS = 0x7c,
15 PCI_DEV_REG3 = 0x80,
16 PCI_DEV_REG4 = 0x84,
17 PCI_DEV_REG5 = 0x88,
18 PCI_CFG_REG_0 = 0x90,
19 PCI_CFG_REG_1 = 0x94,
21 PSM_CONFIG_REG0 = 0x98,
22 PSM_CONFIG_REG1 = 0x9C,
[all …]
H A Dskge.h10 #define PCI_DEV_REG1 0x40
11 #define PCI_PHY_COMA 0x8000000
12 #define PCI_VIO 0x2000000
14 #define PCI_DEV_REG2 0x44
15 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
19 B0_RAP = 0x0000,
20 B0_CTST = 0x0004,
21 B0_LED = 0x0006,
22 B0_POWER_CTRL = 0x0007,
23 B0_ISRC = 0x0008,
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_reg.h62 #define RADEON_MC_AGP_LOCATION 0x014c
63 #define RADEON_MC_AGP_START_MASK 0x0000FFFF
64 #define RADEON_MC_AGP_START_SHIFT 0
65 #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
67 #define RADEON_MC_FB_LOCATION 0x0148
68 #define RADEON_MC_FB_START_MASK 0x0000FFFF
69 #define RADEON_MC_FB_START_SHIFT 0
70 #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
72 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
73 #define RADEON_AGP_BASE 0x0170
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]

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