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12

/linux/sound/soc/codecs/
H A Dmt6351.h12 #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000)
13 #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002)
14 #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004)
15 #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006)
16 #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008)
17 #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a)
18 #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c)
19 #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e)
20 #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010)
21 #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012)
[all …]
H A Dwm5100-tables.c815 { 0x0000, 0x0000 }, /* R0 - software reset */
816 { 0x0001, 0x0000 }, /* R1 - Device Revision */
817 { 0x0010, 0x0801 }, /* R16 - Ctrl IF 1 */
818 { 0x0020, 0x0000 }, /* R32 - Tone Generator 1 */
819 { 0x0030, 0x0000 }, /* R48 - PWM Drive 1 */
820 { 0x0031, 0x0100 }, /* R49 - PWM Drive 2 */
821 { 0x0032, 0x0100 }, /* R50 - PWM Drive 3 */
822 { 0x0100, 0x0002 }, /* R256 - Clocking 1 */
823 { 0x0101, 0x0000 }, /* R257 - Clocking 3 */
824 { 0x0102, 0x0011 }, /* R258 - Clocking 4 */
[all …]
H A Dlpass-rx-macro.c21 #define CDC_RX_TOP_TOP_CFG0 (0x0000)
22 #define CDC_RX_TOP_SWR_CTRL (0x0008)
23 #define CDC_RX_TOP_DEBUG (0x000C)
24 #define CDC_RX_TOP_DEBUG_BUS (0x0010)
25 #define CDC_RX_TOP_DEBUG_EN0 (0x0014)
26 #define CDC_RX_TOP_DEBUG_EN1 (0x0018)
27 #define CDC_RX_TOP_DEBUG_EN2 (0x001C)
28 #define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020)
29 #define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024)
30 #define CDC_RX_TOP_HPHL_COMP_LUT (0x0028)
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-clocks.dtsi9 #clock-cells = <0>;
12 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
16 #clock-cells = <0>;
19 ti,bit-shift = <0x1e>;
20 reg = <0x0d00>;
26 #clock-cells = <0>;
29 ti,bit-shift = <0x1b>;
30 reg = <0x0d00>;
35 #clock-cells = <0>;
38 ti,bit-shift = <0xc>;
[all …]
H A Domap3xxx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
18 reg = <0x0d40>;
22 #clock-cells = <0>;
27 reg = <0x1270>;
32 #clock-cells = <0>;
35 reg = <0x0d70>;
40 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_pcie2.h5 #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
6 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
7 #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
8 #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
9 #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
11 #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
12 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
13 #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
14 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da4xx_gpu.c30 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
61 OUT_RING(ring, 0x00000000); in a4xx_submit()
80 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
82 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
84 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
86 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
[all …]
H A Da5xx_gpu.c75 for (i = 0; i < submit->nr_cmds; i++) { in a5xx_submit_in_rb()
97 for (i = 0; i < dwords; i++) { in a5xx_submit_in_rb()
132 unsigned int i, ibs = 0; in a5xx_submit()
137 ring->cur_ctx_seqno = 0; in a5xx_submit()
143 OUT_RING(ring, 0x02); in a5xx_submit()
147 OUT_RING(ring, 0); in a5xx_submit()
164 OUT_RING(ring, 0x0); in a5xx_submit()
168 OUT_RING(ring, 0x02); in a5xx_submit()
171 for (i = 0; i < submit->nr_cmds; i++) { in a5xx_submit()
195 if ((ibs % 32) == 0) in a5xx_submit()
[all …]
/linux/include/linux/mfd/wcd934x/
H A Dregisters.h6 #define WCD934X_CODEC_RPM_CLK_GATE 0x0002
7 #define WCD934X_CODEC_RPM_CLK_GATE_MASK GENMASK(1, 0)
8 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG 0x0003
9 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0)
11 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0)
12 #define WCD934X_CODEC_RPM_RST_CTL 0x0009
13 #define WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL 0x0011
14 #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0 0x0021
15 #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2 0x0023
16 #define WCD934X_CHIP_TIER_CTRL_EFUSE_CTL 0x0025
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h13 #define SXGBE_CORE_TX_CONFIG_REG 0x0000
14 #define SXGBE_CORE_RX_CONFIG_REG 0x0004
15 #define SXGBE_CORE_PKT_FILTER_REG 0x0008
16 #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
17 #define SXGBE_CORE_HASH_TABLE_REG0 0x0010
18 #define SXGBE_CORE_HASH_TABLE_REG1 0x0014
19 #define SXGBE_CORE_HASH_TABLE_REG2 0x0018
20 #define SXGBE_CORE_HASH_TABLE_REG3 0x001C
21 #define SXGBE_CORE_HASH_TABLE_REG4 0x0020
22 #define SXGBE_CORE_HASH_TABLE_REG5 0x0024
[all …]
/linux/drivers/media/pci/solo6x10/
H A Dsolo6x10-regs.h20 #define SOLO_SYS_CFG 0x0000
21 #define SOLO_SYS_CFG_FOUT_EN 0x00000001
22 #define SOLO_SYS_CFG_PLL_BYPASS 0x00000002
23 #define SOLO_SYS_CFG_PLL_PWDN 0x00000004
24 #define SOLO_SYS_CFG_OUTDIV(__n) (((__n) & 0x003) << 3)
25 #define SOLO_SYS_CFG_FEEDBACKDIV(__n) (((__n) & 0x1ff) << 5)
26 #define SOLO_SYS_CFG_INPUTDIV(__n) (((__n) & 0x01f) << 14)
27 #define SOLO_SYS_CFG_CLOCK_DIV 0x00080000
28 #define SOLO_SYS_CFG_NCLK_DELAY(__n) (((__n) & 0x003) << 24)
29 #define SOLO_SYS_CFG_PCLK_DELAY(__n) (((__n) & 0x00f) << 26)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-reg.h15 #define AUDIO_TOP_CON0 (0x0000)
16 #define AUDIO_TOP_CON1 (0x0004)
17 #define AUDIO_TOP_CON2 (0x0008)
18 #define AUDIO_TOP_CON3 (0x000c)
20 #define AFE_DAC_CON0 (0x0010)
21 #define AFE_DAC_CON1 (0x0014)
22 #define AFE_I2S_CON (0x0018)
23 #define AFE_CONN0 (0x0020)
24 #define AFE_CONN1 (0x0024)
25 #define AFE_CONN2 (0x0028)
[all …]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-common.h12 #define DMA_MR 0x3000
13 #define DMA_SBMR 0x3004
14 #define DMA_ISR 0x3008
15 #define DMA_AXIARCR 0x3010
16 #define DMA_AXIAWCR 0x3018
17 #define DMA_AXIAWARCR 0x301c
18 #define DMA_DSR0 0x3020
19 #define DMA_DSR1 0x3024
20 #define DMA_TXEDMACR 0x3040
21 #define DMA_RXEDMACR 0x3044
[all …]
/linux/include/video/
H A Dradeon.h6 #define RADEON_REGSIZE 0x4000
9 #define MM_INDEX 0x0000
10 #define MM_DATA 0x0004
11 #define BUS_CNTL 0x0030
12 #define HI_STAT 0x004C
13 #define BUS_CNTL1 0x0034
14 #define I2C_CNTL_1 0x0094
15 #define CNFG_CNTL 0x00E0
16 #define CNFG_MEMSIZE 0x00F8
17 #define CNFG_APER_0_BASE 0x0100
[all …]
/linux/drivers/usb/gadget/udc/
H A Drenesas_usbf.c28 #define USBF_REG_USB_CONTROL 0x000
40 #define USBF_REG_USB_STATUS 0x004
49 #define USBF_REG_USB_ADDRESS 0x008
52 #define USBF_USB_GET_FRAME(_r) ((_r) & 0x7FF)
54 #define USBF_REG_SETUP_DATA0 0x018
55 #define USBF_REG_SETUP_DATA1 0x01C
56 #define USBF_REG_USB_INT_STA 0x020
63 #define USBF_USB_EPN_INT(_n) (BIT(8) << (_n)) /* n=0..15 */
65 #define USBF_REG_USB_INT_ENA 0x024
72 #define USBF_USB_EPN_EN(_n) (BIT(8) << (_n)) /* n=0..15 */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_offset.h29 // base address: 0x60000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_reg.h62 #define RADEON_MC_AGP_LOCATION 0x014c
63 #define RADEON_MC_AGP_START_MASK 0x0000FFFF
64 #define RADEON_MC_AGP_START_SHIFT 0
65 #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
67 #define RADEON_MC_FB_LOCATION 0x0148
68 #define RADEON_MC_FB_START_MASK 0x0000FFFF
69 #define RADEON_MC_FB_START_SHIFT 0
70 #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
72 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
73 #define RADEON_AGP_BASE 0x0170
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h10 #define PCI_DEV_REG1 0x40
11 #define PCI_PHY_COMA 0x8000000
12 #define PCI_VIO 0x2000000
14 #define PCI_DEV_REG2 0x44
15 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
19 B0_RAP = 0x0000,
20 B0_CTST = 0x0004,
21 B0_LED = 0x0006,
22 B0_POWER_CTRL = 0x0007,
23 B0_ISRC = 0x0008,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]
H A Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_2_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_4_3_offset.h29 // base address: 0x8000
30 …GRBM_CNTL 0x0000
31 …e regGRBM_CNTL_BASE_IDX 0
32 …GRBM_SKEW_CNTL 0x0001
33 …e regGRBM_SKEW_CNTL_BASE_IDX 0
34 …GRBM_STATUS2 0x0002
35 …e regGRBM_STATUS2_BASE_IDX 0
36 …GRBM_PWR_CNTL 0x0003
37 …e regGRBM_PWR_CNTL_BASE_IDX 0
38 …GRBM_STATUS 0x0004
[all …]
H A Dgc_9_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]

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