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/freebsd/sys/arm/arm/
H A Ddisassem.c76 * m - m register (bits 0-3)
81 * h - 3rd fp operand (register/immediate) (bits 0-4)
83 * t - thumb branch address (bits 24, 0-23)
84 * k - breakpoint comment (bits 0-3, 8-19)
87 * c - comment field bits(0-23)
112 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
113 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
114 { 0x0f000000, 0x0f000000, "swi", "c" },
115 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */
116 { 0x0f000000, 0x0a000000, "b", "b" },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spmi/
H A Dqcom,x1e80100-spmi-pmic-arb.yaml46 minimum: 0
53 minimum: 0
86 cell 1: slave ID for the requested interrupt (0-15)
87 cell 2: peripheral ID for requested interrupt (0-255)
88 cell 3: the requested peripheral interrupt (0-7)
110 reg = <0 0x0c400000 0 0x3000>,
111 <0 0x0c500000 0 0x4000000>,
112 <0 0x0c440000 0 0x80000>;
115 qcom,ee = <0>;
116 qcom,channel = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdx75.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 0>;
80 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #size-cells = <0>;
67 CPU0: cpu@0 {
70 reg = <0 0>;
71 clocks = <&cpufreq_hw 0>;
76 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0 0x100>;
[all …]
H A Dsm8450.dtsi39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8650.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
59 #clock-cells = <0>;
69 #size-cells = <0>;
71 CPU0: cpu@0 {
74 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0 0x100>;
[all …]
H A Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 CPU0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
13 def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
15 SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
16 def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
18 def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>,
20 SDTCisSameAs<0, 2>,
22 def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>,
23 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
24 def SDT_loongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>,
25 SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>;
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]