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/linux/arch/sh/drivers/pci/
H A Dfixups-rts7751r2d.c17 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
18 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
44 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
48 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM); in pci_fixup_pcic()
49 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM); in pci_fixup_pcic()
51 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1); in pci_fixup_pcic()
52 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4); in pci_fixup_pcic()
58 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic()
59 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic()
60 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic()
[all …]
H A Dfixups-landisk.c18 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
19 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
29 int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0); in pcibios_map_platform_irq()
31 if ((slot | (pin - 1)) > 0x3) { in pcibios_map_platform_irq()
44 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
51 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic()
52 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic()
53 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic()
54 pci_write_reg(chan, 0x00000000, SH4_PCILAR1); in pci_fixup_pcic()
56 return 0; in pci_fixup_pcic()
H A Dfixups-se7751.c14 case 0: return evt2irq(0x3a0); in pcibios_map_platform_irq()
15 case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */ in pcibios_map_platform_irq()
25 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
26 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
58 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ in pci_fixup_pcic()
61 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
72 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); in pci_fixup_pcic()
73 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); in pci_fixup_pcic()
76 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */ in pci_fixup_pcic()
77 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ in pci_fixup_pcic()
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
/linux/arch/powerpc/boot/dts/
H A Dgamecube.dts24 reg = <0x00000000 0x01800000>;
29 #size-cells = <0>;
31 PowerPC,gekko@0 {
33 reg = <0>;
49 ranges = <0x0c000000 0x0c000000 0x00010000>;
54 reg = <0x0c002000 0x100>;
60 reg = <0x0c003000 0x100>;
73 reg = <0x0c005000 0x200>;
76 memory@0 {
78 reg = <0 0x1000000>; /* 16MB */
[all …]
H A Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/linux/arch/m68k/include/asm/
H A Dsun3mmu.h25 #define SUN3_CONTROL_MASK (0x0FFFFFFC)
29 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
30 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
31 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
32 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
33 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
34 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
35 #define AC_BUS_ERROR 0x60000000 /* 34 Cleared on read, byte. */
36 #define AC_SYNC_ERR 0x60000000 /* c fault type */
37 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
[all …]
/linux/drivers/net/ethernet/pasemi/
H A Dpasemi_mac.h110 PAS_MAC_CFG_PCFG = 0x80,
111 PAS_MAC_CFG_MACCFG = 0x84,
112 PAS_MAC_CFG_ADR0 = 0x8c,
113 PAS_MAC_CFG_ADR1 = 0x90,
114 PAS_MAC_CFG_TXP = 0x98,
115 PAS_MAC_CFG_RMON = 0x100,
116 PAS_MAC_IPC_CHNL = 0x208,
120 #define PAS_MAC_CFG_PCFG_PE 0x80000000
121 #define PAS_MAC_CFG_PCFG_CE 0x40000000
122 #define PAS_MAC_CFG_PCFG_BU 0x20000000
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2e.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
64 reg = <0x2620750 24>;
72 reg = <0x25000000 0x10000>;
83 reg = <0x25010000 0x70000>;
91 reg = <0x0c000000 0x200000>;
92 ranges = <0x0 0x0c000000 0x200000>;
97 reg = <0x001f0000 0x8000>;
107 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml58 Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
81 0x0 - MC portals
82 0x1 - QBMAN portals
140 const: 0
161 reg = <0x0c000000 0x40>, /* MC portal base */
162 <0x08340000 0x40000>; /* MC control reg */
164 * Region type 0x0 - MC portals
165 * Region type 0x1 - QBMAN portals
167 ranges = <0x0 0x0 0x8 0x0c000000 0x4000000
168 0x1 0x0 0x8 0x18000000 0x8000000>;
[all …]
/linux/tools/testing/kunit/qemu_configs/
H A Dsh.py7 CONFIG_MEMORY_START=0x0c000000
/linux/arch/sh/include/cpu-sh4/cpu/
H A Daddrspace.h10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
/linux/arch/sh/configs/
H A Dse7751_defconfig10 CONFIG_MEMORY_START=0x0c000000
H A Dse7705_defconfig10 CONFIG_MEMORY_START=0x0c000000
11 CONFIG_MEMORY_SIZE=0x02000000
H A Dse7750_defconfig12 CONFIG_MEMORY_START=0x0c000000
13 CONFIG_MEMORY_SIZE=0x02000000
H A Dsh7710voipgw_defconfig13 CONFIG_MEMORY_START=0x0c000000
14 CONFIG_MEMORY_SIZE=0x00800000
H A Drsk7269_defconfig8 CONFIG_MEMORY_START=0x0c000000
9 CONFIG_MEMORY_SIZE=0x02000000
H A Dse7619_defconfig12 CONFIG_MEMORY_START=0x0c000000
H A Dshmin_defconfig16 CONFIG_MEMORY_START=0x0c000000
17 CONFIG_MEMORY_SIZE=0x00800000
23 …onsole=ttySC1,115200 root=1f01 mtdparts=phys_mapped_flash:64k(firm)ro,-(sys) netdev=34,0x300,eth0 "
H A Dse7722_defconfig12 CONFIG_MEMORY_START=0x0c000000
H A Dlboxre2_defconfig9 CONFIG_MEMORY_START=0x0c000000
H A Ddreamcast_defconfig9 CONFIG_MEMORY_START=0x0c000000
10 CONFIG_MEMORY_SIZE=0x01000000
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv50.c36 case 0x50: /* it exists, but only has bit 31, not the dividers.. */ in read_div()
37 case 0x84: in read_div()
38 case 0x86: in read_div()
39 case 0x98: in read_div()
40 case 0xa0: in read_div()
41 return nvkm_rd32(device, 0x004700); in read_div()
42 case 0x92: in read_div()
43 case 0x94: in read_div()
44 case 0x96: in read_div()
45 return nvkm_rd32(device, 0x004800); in read_div()
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/linux/arch/arm/mach-pxa/
H A Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]

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