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/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_init.c61 if (cond[0] == 0) in r92c_check_condition()
65 "%s: condition byte 0: %02X; chip %02X, board %02X\n", in r92c_check_condition()
66 __func__, cond[0], rs->chip, rs->board_type); in r92c_check_condition()
82 for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++) in r92c_check_condition()
86 return (0); in r92c_check_condition()
94 /* Reserve pages [0; page_count]. */ in r92c_llt_init()
95 for (i = 0; i < sc->page_count; i++) { in r92c_llt_init()
96 if ((error = r92c_llt_write(sc, i, i + 1)) != 0) in r92c_llt_init()
99 /* NB: 0xff indicates end-of-list. */ in r92c_llt_init()
100 if ((error = r92c_llt_write(sc, i, 0xff)) != 0) in r92c_llt_init()
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dgamecube.dts24 reg = <0x00000000 0x01800000>;
29 #size-cells = <0>;
31 PowerPC,gekko@0 {
33 reg = <0>;
49 ranges = <0x0c000000 0x0c000000 0x00010000>;
54 reg = <0x0c002000 0x100>;
60 reg = <0x0c003000 0x100>;
73 reg = <0x0c005000 0x200>;
76 memory@0 {
78 reg = <0 0x1000000>; /* 16MB */
[all …]
H A Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/freebsd/sys/contrib/ncsw/Peripherals/FM/Pcd/
H A Dfm_plcr.h49 #define FM_PCD_PLCR_PAR_GO 0x80000000
50 #define FM_PCD_PLCR_PAR_PWSEL_MASK 0x0000FFFF
51 #define FM_PCD_PLCR_PAR_R 0x40000000
57 #define FM_PCD_PLCR_PEMODE_PI 0x80000000
58 #define FM_PCD_PLCR_PEMODE_CBLND 0x40000000
59 #define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000
60 #define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000
61 #define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000
62 #define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000
63 #define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2e.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
64 reg = <0x2620750 24>;
72 reg = <0x25000000 0x10000>;
83 reg = <0x25010000 0x70000>;
91 reg = <0x0c000000 0x200000>;
92 ranges = <0x0 0x0c000000 0x200000>;
97 reg = <0x001f0000 0x8000>;
107 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
[all …]
H A Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x8000>;
78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
[all …]
H A Dkeystone-k2l.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
49 reg = <0x02348400 0x100>;
59 reg = <0x02348800 0x100>;
66 reg = <0x02348000 0x100>;
110 reg = <0x0262069
[all...]
H A Dkeystone-k2g.dtsi33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
46 reg = <0x0 0x02561000 0x0 0x1000>,
47 <0x0 0x02562000 0x0 0x2000>,
48 <0x0 0x02564000 0x0 0x2000>,
49 <0x0 0x02566000 0x0 0x2000>;
74 #size-cells = <0>;
77 usb0_phy: usb-phy@0 {
79 reg = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dfsl,qoriq-mc.txt47 Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
71 0x0 - MC portals
72 0x1 - QBMAN portals
99 have a value of 0.
154 stream-match-mask = <0x7C00>;
170 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
171 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
180 * Region type 0x0 - MC portals
181 * Region type 0x1 - QBMAN portals
183 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/freebsd/sys/dev/alc/
H A Dif_alcreg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dsamsung,exynos-pcie.yaml97 reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
107 pinctrl-0 = <&pcie_bus &pcie_wlanen>;
111 bus-range = <0x00 0xff>;
112 ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
113 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
116 interrupt-map-mask = <0 0 0 0>;
117 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6dl-colibri-eval-v3.dts37 #clock-cells = <0>;
47 mcp251x0: mcp251x@0 {
51 interrupts = <27 0x2>;
52 reg = <0>;
67 reg = <0x68>;
73 pinctrl-0 = <
132 ranges = <0 0 0x08000000 0x02000000
133 1 0 0x0a000000 0x02000000
134 2 0 0x0c000000 0x02000000
135 3 0 0x0e000000 0x02000000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dimx-weim.txt25 <cs-number> 0 <physical address of mapping> <size>
32 register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
36 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
38 05 128M 0M 0M 0M
39 033 64M 64M 0M 0M
40 0113 64M 32M 32M 0M
44 what bootloader sets up in IOMUXC_GPR1[11:0] will be
75 reg = <0x021b8000 0x4000>;
79 ranges = <0 0 0x08000000 0x08000000>;
82 nor@0,0 {
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210desc.h31 uint32_t ds_ctl0; /* DMA control 0 */
33 uint32_t ds_status0; /* DMA status 0 */
40 #define AR_FrameLen 0x00000fff /* frame length */
41 #define AR_HdrLen 0x0003f000 /* header length */
43 #define AR_XmitRate 0x003c0000 /* txrate */
45 #define AR_Rate_6M 0xb
46 #define AR_Rate_9M 0xf
47 #define AR_Rate_12M 0xa
48 #define AR_Rate_18M 0xe
49 #define AR_Rate_24M 0x9
[all …]
/freebsd/sys/dev/et/
H A Dif_etvar.h74 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff)
83 #define ET_TDCTRL1_LEN_MASK 0x0000FFFF
85 #define ET_TDCTRL2_LAST_FRAG 0x00000001
86 #define ET_TDCTRL2_FIRST_FRAG 0x00000002
87 #define ET_TDCTRL2_INTR 0x00000004
88 #define ET_TDCTRL2_CTRL_WORD 0x00000008
89 #define ET_TDCTRL2_HDX_BACKP 0x00000010
90 #define ET_TDCTRL2_XMIT_PAUSE 0x00000020
91 #define ET_TDCTRL2_FRAME_ERR 0x00000040
92 #define ET_TDCTRL2_NO_CRC 0x00000080
[all …]
/freebsd/sys/dev/safe/
H A Dsafereg.h37 #define BS_BAR 0x10 /* DMA base address register */
38 #define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
39 #define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
41 #define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */
44 #define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */
46 #define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */
47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */
50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dfoundation-v8.dtsi12 /memreserve/ 0x80000000 0x00010000;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
43 reg = <0x0 0x1>;
49 reg = <0x0 0x2>;
55 reg = <0x0 0x3>;
68 reg = <0x00000000 0x80000000 0 0x80000000>,
69 <0x00000008 0x80000000 0 0x80000000>;
96 reg = <0x0 0x2a440000 0 0x1000>,
[all …]
H A Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
[all …]
/freebsd/sys/dev/sound/macio/
H A Ddavbusreg.h36 #define DAVBUS_SOUND_CTRL 0x00
37 #define DAVBUS_CODEC_CTRL 0x10
38 #define DAVBUS_CODEC_STATUS 0x20
39 #define DAVBUS_CLIP_COUNT 0x30
40 #define DAVBUS_BYTE_SWAP 0x40
44 * but the controller itself uses subframe 0 to communicate with the codec.
49 #define DAVBUS_INPUT_SUBFRAME0 0x00000001
50 #define DAVBUS_INPUT_SUBFRAME1 0x00000002
51 #define DAVBUS_INPUT_SUBFRAME2 0x00000004
52 #define DAVBUS_INPUT_SUBFRAME3 0x00000008
[all …]
/freebsd/sys/dev/rtwn/rtl8192e/
H A Dr92e_chan.c72 if (chan <= 2) group = 0; in r92e_get_power_group()
78 KASSERT(0, ("wrong 2GHz channel %d!\n", chan)); in r92e_get_power_group()
82 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags)); in r92e_get_power_group()
123 pwr = power[ridx] + rs->ofdm_tx_pwr_diff_2g[chain][0]; in r92e_get_txpower()
124 if (pwr < 0) in r92e_get_txpower()
125 pwr = 0; in r92e_get_txpower()
130 for (i = 0; i < sc->ntxchains; i++) { in r92e_get_txpower()
143 if (pwr < 0) in r92e_get_txpower()
144 pwr = 0; in r92e_get_txpower()
162 for (i = 0;
[all...]
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr7s9210-rza2mevb.dts27 * | 1 2 3 4 5 6 7 8 9 0 | SW6-6 set to VDC6
55 pinctrl-0 = <&keyboard_pins>;
59 interrupts = <0 IRQ_TYPE_EDGE_BOTH>;
70 gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
79 reg = <0x0c000000 0x04000000>; /* SDRAM */
93 pinctrl-0 = <&eth1_pins>;
100 reg = <0>;
114 pinctrl-0
[all...]

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