Searched +full:0 +full:x0ae96900 (Results 1 – 8 of 8) sorted by relevance
/freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
H A D | qcom,sm8450-mdss.yaml | 39 "^display-controller@[0-9a-f]+$": 47 "^displayport-controller@[0-9a-f]+$": 57 "^dsi@[0-9a-f]+$": 67 "^phy@[0-9a-f]+$": 91 reg = <0x0ae00000 0x1000>; 115 iommus = <&apps_smmu 0x2800 0x402>; 123 reg = <0x0ae01000 0x8f00 [all...] |
H A D | qcom,sm8150-mdss.yaml | 48 "^display-controller@[0-9a-f]+$": 56 "^displayport-controller@[0-9a-f]+$": 65 "^dsi@[0-9a-f]+$": 75 "^phy@[0-9a-f]+$": 96 reg = <0x0ae00000 0x1000>; 115 iommus = <&apps_smmu 0x800 0x420>; 123 reg = <0x0ae01000 0x8f000>, 124 <0x0aeb0000 0x2008>; 140 interrupts = <0>; 144 #size-cells = <0>; [all …]
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H A D | qcom,sm8250-mdss.yaml | 47 "^display-controller@[0-9a-f]+$": 55 "^displayport-controller@[0-9a-f]+$": 65 "^dsi@[0-9a-f]+$": 75 "^phy@[0-9a-f]+$": 99 reg = <0x0ae00000 0x1000>; 118 iommus = <&apps_smmu 0x820 0x402>; 126 reg = <0x0ae01000 0x8f00 [all...] |
/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | sc8180x.dtsi | 29 #clock-cells = <0>; 35 #clock-cells = <0>; 43 #size-cells = <0>; 45 CPU0: cpu@0 { 48 reg = <0x0 0x0>; 52 qcom,freq-domain = <&cpufreq_hw 0>; 59 clocks = <&cpufreq_hw 0>; 77 reg = <0x0 0x100>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 88 clocks = <&cpufreq_hw 0>; [all …]
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H A D | sm8350.dtsi | 38 #clock-cells = <0>; 46 #clock-cells = <0>; 52 #size-cells = <0>; 54 CPU0: cpu@0 { 57 reg = <0x0 0x0>; 58 clocks = <&cpufreq_hw 0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 85 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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H A D | sm8150.dtsi | 34 #clock-cells = <0>; 41 #clock-cells = <0>; 49 #size-cells = <0>; 51 CPU0: cpu@0 { 54 reg = <0x0 0x0>; 55 clocks = <&cpufreq_hw 0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 83 reg = <0x0 0x100>; 84 clocks = <&cpufreq_hw 0>; [all …]
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H A D | sm8450.dtsi | 39 #clock-cells = <0>; 45 #clock-cells = <0>; 52 #size-cells = <0>; 54 CPU0: cpu@0 { 57 reg = <0x0 0x0>; 62 qcom,freq-domain = <&cpufreq_hw 0>; 64 clocks = <&cpufreq_hw 0>; 81 reg = <0x0 0x100>; 86 qcom,freq-domain = <&cpufreq_hw 0>; 88 clocks = <&cpufreq_hw 0>; [all …]
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H A D | sm8250.dtsi | 80 #clock-cells = <0>; 88 #clock-cells = <0>; 94 #size-cells = <0>; 96 CPU0: cpu@0 { 99 reg = <0x0 0x0>; 100 clocks = <&cpufreq_hw 0>; 107 qcom,freq-domain = <&cpufreq_hw 0>; 109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 115 cache-size = <0x20000>; 121 cache-size = <0x400000>; [all …]
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