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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,sc7280-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
82 interrupts = <0>;
88 #size-cells = <0>;
90 port@0 {
91 reg = <0>;
H A Dqcom,sdm845-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
75 interrupts = <0>;
81 #size-cells = <0>;
83 port@0 {
84 reg = <0>;
H A Dqcom,sm8150-dpu.yaml54 reg = <0x0ae01000 0x8f000>,
55 <0x0aeb0000 0x2008>;
71 interrupts = <0>;
75 #size-cells = <0>;
77 port@0 {
78 reg = <0>;
H A Dqcom,sm8250-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
78 interrupts = <0>;
82 #size-cells = <0>;
84 port@0 {
85 reg = <0>;
H A Dqcom,sc7180-dpu.yaml87 reg = <0x0ae01000 0x8f000>,
88 <0x0aeb0000 0x2008>;
102 interrupts = <0>;
108 #size-cells = <0>;
110 port@0 {
111 reg = <0>;
H A Dqcom,sc8280xp-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
87 interrupts = <0>;
91 #size-cells = <0>;
93 port@0 {
94 reg = <0>;
H A Dqcom,sm8350-dpu.yaml58 reg = <0x0ae01000 0x8f000>,
59 <0x0aeb0000 0x2008>;
82 interrupts = <0>;
86 #size-cells = <0>;
88 port@0 {
89 reg = <0>;
H A Dqcom,sm8550-dpu.yaml64 reg = <0x0ae01000 0x8f000>,
65 <0x0aeb0000 0x2008>;
88 interrupts = <0>;
92 #size-cells = <0>;
94 port@0 {
95 reg = <0>;
H A Dqcom,sm8650-dpu.yaml62 reg = <0x0ae01000 0x8f000>,
63 <0x0aeb0000 0x2008>;
84 interrupts = <0>;
88 #size-cells = <0>;
90 port@0 {
91 reg = <0>;
H A Dqcom,sm8450-dpu.yaml65 reg = <0x0ae01000 0x8f000>,
66 <0x0aeb0000 0x2008>;
89 interrupts = <0>;
93 #size-cells = <0>;
95 port@0 {
96 reg = <0>;
H A Dqcom,sm7150-dpu.yaml62 reg = <0x0ae01000 0x8f000>,
63 <0x0aeb0000 0x2008>;
86 interrupts = <0>;
90 #size-cells = <0>;
92 port@0 {
93 reg = <0>;
H A Dqcom,sc8280xp-mdss.yaml35 "^display-controller@[0-9a-f]+$":
43 "^displayport-controller@[0-9a-f]+$":
65 reg = <0x0ae00000 0x1000>;
83 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
84 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
87 iommus = <&apps_smmu 0x1000 0x40
[all...]
H A Ddpu-sdm845.yaml65 "^display-controller@[0-9a-f]+$":
118 port@0:
127 - port@0
164 reg = <0x0ae00000 0x1000>;
176 iommus = <&apps_smmu 0x880 0x8>,
177 <&apps_smmu 0xc80 0x8>;
182 reg = <0x0ae01000 0x8f000>,
183 <0x0aeb0000 0x2008>;
193 interrupts = <0>;
199 #size-cells = <0>;
[all …]
H A Ddpu-sc7180.yaml73 "^display-controller@[0-9a-f]+$":
130 port@0:
139 - port@0
176 reg = <0xae00000 0x1000>;
191 iommus = <&apps_smmu 0x800 0x2>;
196 reg = <0x0ae01000 0x8f000>,
197 <0x0aeb0000 0x2008>;
211 interrupts = <0>;
217 #size-cells = <0>;
219 port@0 {
[all …]
H A Ddpu-sc7280.yaml72 "^display-controller@[0-9a-f]+$":
128 port@0:
137 - port@0
174 reg = <0xae00000 0x1000>;
191 iommus = <&apps_smmu 0x900 0x402>;
196 reg = <0x0ae01000 0x8f000>,
197 <0x0aeb0000 0x2008>;
215 interrupts = <0>;
221 #size-cells = <0>;
223 port@0 {
[all …]
H A Dqcom,x1e80100-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^phy@[0-9a-f]+$":
74 reg = <0x0ae00000 0x1000>;
77 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
78 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
79 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
95 iommus = <&apps_smmu 0x1c00 0x2>;
103 reg = <0x0ae01000 0x8f000>,
104 <0x0aeb0000 0x2008>;
[all …]
H A Dqcom,sm6350-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
95 reg = <0x0ae00000 0x1000>;
109 iommus = <&apps_smmu 0x800 0x2>;
116 reg = <0x0ae01000 0x8f000>,
117 <0x0aeb0000 0x2008>;
139 interrupts = <0>;
145 #size-cells = <0>;
[all …]
H A Dqcom,sm8350-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
96 reg = <0x0ae00000 0x1000>;
99 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
100 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
[all...]
H A Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x
[all...]
H A Dqcom,sc7180-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
101 reg = <0xae00000 0x1000>;
118 iommus = <&apps_smmu 0x800 0x2>;
123 reg = <0x0ae01000
[all...]
H A Dqcom,sm8650-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
81 reg = <0x0ae00000 0x1000>;
97 iommus = <&apps_smmu 0x1c00 0x2>;
105 reg = <0x0ae01000 0x8f000>,
106 <0x0aeb0000 0x2008>;
127 interrupts = <0>;
131 #size-cells = <0>;
[all …]
H A Dqcom,sm8450-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x2800 0x402>;
123 reg = <0x0ae01000
[all...]
H A Dqcom,sm8550-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
94 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
95 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
[all...]
H A Dqcom,sm8150-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
96 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x800 0x420>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
140 interrupts = <0>;
144 #size-cells = <0>;
[all …]
H A Dqcom,sm8250-mdss.yaml47 "^display-controller@[0-9a-f]+$":
55 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
99 reg = <0x0ae00000 0x1000>;
118 iommus = <&apps_smmu 0x820 0x402>;
126 reg = <0x0ae01000
[all...]

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