Searched +full:0 +full:x0aaf0000 (Results 1 – 6 of 6) sorted by relevance
17 #define VID_CTL 0x0018 #define VID_ALP 0x0419 #define VID_CLF 0x0820 #define VID_VPO 0x0C21 #define VID_VPS 0x1022 #define VID_KEY1 0x2823 #define VID_KEY2 0x2C24 #define VID_MPR0 0x3025 #define VID_MPR1 0x3426 #define VID_MPR2 0x38[all …]
35 #clock-cells = <0>;43 #clock-cells = <0>;49 #size-cells = <0>;51 cpu0: cpu@0 {54 reg = <0x0 0x0>;55 clocks = <&cpufreq_hw 0>;60 qcom,freq-domain = <&cpufreq_hw 0>;84 reg = <0x0 0x100>;85 clocks = <&cpufreq_hw 0>;90 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
40 #clock-cells = <0>;46 #clock-cells = <0>;53 #size-cells = <0>;55 cpu0: cpu@0 {58 reg = <0x0 0x0>;63 qcom,freq-domain = <&cpufreq_hw 0>;65 clocks = <&cpufreq_hw 0>;82 reg = <0x0 0x100>;87 qcom,freq-domain = <&cpufreq_hw 0>;89 clocks = <&cpufreq_hw 0>;[all …]
40 #clock-cells = <0>;45 #clock-cells = <0>;49 #clock-cells = <0>;57 #clock-cells = <0>;67 #size-cells = <0>;69 cpu0: cpu@0 {72 reg = <0 0>;73 clocks = <&cpufreq_hw 0>;78 qcom,freq-domain = <&cpufreq_hw 0>;98 reg = <0 0x100>;[all …]
83 #clock-cells = <0>;89 #clock-cells = <0>;100 reg = <0x0 0x004cd000 0x0 0x1000>;104 reg = <0x0 0x80000000 0x0 0x600000>;109 reg = <0x0 0x80600000 0x0 0x200000>;114 reg = <0x0 0x80800000 0x0 0x60000>;119 reg = <0x0 0x80860000 0x0 0x20000>;125 reg = <0x0 0x80884000 0x0 0x10000>;130 reg = <0x0 0x808ff000 0x0 0x1000>;135 reg = <0x0 0x80900000 0x0 0x200000>;[all …]
42 #clock-cells = <0>;47 #clock-cells = <0>;52 #clock-cells = <0>;61 #clock-cells = <0>;71 #size-cells = <0>;73 cpu0: cpu@0 {76 reg = <0 0>;78 clocks = <&cpufreq_hw 0>;88 qcom,freq-domain = <&cpufreq_hw 0>;118 reg = <0 0x100>;[all …]