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/linux/drivers/mfd/
H A Dwm8994-regmap.c18 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20 { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21 { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22 { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23 { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24 { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25 { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26 { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27 { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/drivers/net/wireless/ath/carl9170/
H A Dphy.h24 #define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800)
28 #define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000)
29 #define AR9170_PHY_TEST_AGC_CLR 0x10000000
30 #define AR9170_PHY_TEST_RFSILENT_BB 0x00002000
32 #define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004)
33 #define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001
34 #define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002
35 #define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004
36 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008
37 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010
[all …]
/linux/include/linux/mfd/wcd934x/
H A Dregisters.h6 #define WCD934X_CODEC_RPM_CLK_GATE 0x0002
7 #define WCD934X_CODEC_RPM_CLK_GATE_MASK GENMASK(1, 0)
8 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG 0x0003
9 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0)
11 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0)
12 #define WCD934X_CODEC_RPM_RST_CTL 0x0009
13 #define WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL 0x0011
14 #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0 0x0021
15 #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2 0x0023
16 #define WCD934X_CHIP_TIER_CTRL_EFUSE_CTL 0x0025
[all …]
/linux/include/linux/mfd/mt6328/
H A Dregisters.h10 #define MT6328_STRUP_CON0 0x0000
11 #define MT6328_STRUP_CON2 0x0002
12 #define MT6328_STRUP_CON3 0x0004
13 #define MT6328_STRUP_CON4 0x0006
14 #define MT6328_STRUP_CON5 0x0008
15 #define MT6328_STRUP_CON6 0x000a
16 #define MT6328_STRUP_CON7 0x000c
17 #define MT6328_STRUP_CON8 0x000e
18 #define MT6328_STRUP_CON9 0x0010
19 #define MT6328_STRUP_CON10 0x0012
[all …]
/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h19 #define SMIAPP_REG_U16_MODEL_ID CCI_REG16(0x0000)
20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
25 #define SMIAPP_REG_U16_DATA_PEDESTAL CCI_REG16(0x0008)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_d.h26 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE
27 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE
28 #define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE
29 #define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE
30 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE
31 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE
32 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E
33 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E
34 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E
35 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E
[all …]
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-reg.h15 #define AUDIO_TOP_CON0 (0x0000)
16 #define AUDIO_TOP_CON1 (0x0004)
17 #define AUDIO_TOP_CON2 (0x0008)
18 #define AUDIO_TOP_CON3 (0x000c)
20 #define AFE_DAC_CON0 (0x0010)
21 #define AFE_DAC_CON1 (0x0014)
22 #define AFE_I2S_CON (0x0018)
23 #define AFE_CONN0 (0x0020)
24 #define AFE_CONN1 (0x0024)
25 #define AFE_CONN2 (0x0028)
[all …]
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h16 #define ID_REV (0x00)
17 #define ID_REV_ID_MASK_ (0xFFFF0000)
18 #define ID_REV_ID_LAN7430_ (0x74300000)
19 #define ID_REV_ID_LAN7431_ (0x74310000)
20 #define ID_REV_ID_LAN743X_ (0x74300000)
21 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
22 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
23 #define ID_REV_ID_A0X1_ (0xA0010000)
25 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
26 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
[all …]
/linux/drivers/usb/serial/
H A Dipaq.c37 { USB_DEVICE(0x0104, 0x00BE) }, /* Socket USB Sync */
38 { USB_DEVICE(0x03F0, 0x1016) }, /* HP USB Sync */
39 { USB_DEVICE(0x03F0, 0x1116) }, /* HP USB Sync 1611 */
40 { USB_DEVICE(0x03F0, 0x1216) }, /* HP USB Sync 1612 */
41 { USB_DEVICE(0x03F0, 0x2016) }, /* HP USB Sync 1620 */
42 { USB_DEVICE(0x03F0, 0x2116) }, /* HP USB Sync 1621 */
43 { USB_DEVICE(0x03F0, 0x2216) }, /* HP USB Sync 1622 */
44 { USB_DEVICE(0x03F0, 0x3016) }, /* HP USB Sync 1630 */
45 { USB_DEVICE(0x03F0, 0x3116) }, /* HP USB Sync 1631 */
46 { USB_DEVICE(0x03F0, 0x3216) }, /* HP USB Sync 1632 */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_2_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
30 …DAGB0_RDCLI1 0x0001
32 …DAGB0_RDCLI2 0x0002
34 …DAGB0_RDCLI3 0x0003
36 …DAGB0_RDCLI4 0x0004
38 …DAGB0_RDCLI5 0x0005
40 …DAGB0_RDCLI6 0x0006
42 …DAGB0_RDCLI7 0x0007
44 …DAGB0_RDCLI8 0x0008
[all …]
H A Dmmhub_1_7_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c29 #define UDPHY_PCS 0x4000
30 #define UDPHY_PMA 0x8000
38 #define DP_LANE_SEL_ALL GENMASK(7, 0)
41 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
45 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
47 #define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */
51 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
53 #define CMN_LCPLL_SSC_EN BIT(0)
55 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
59 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
[all …]
/linux/sound/soc/codecs/
H A Dwm8962.c101 return 0; \
104 WM8962_REGULATOR_EVENT(0)
114 { 0, 0x009F }, /* R0 - Left Input volume */
115 { 1, 0x049F }, /* R1 - Right Input volume */
116 { 2, 0x0000 }, /* R2 - HPOUTL volume */
117 { 3, 0x0000 }, /* R3 - HPOUTR volume */
119 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
120 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
121 { 7, 0x000A }, /* R7 - Audio Interface 0 */
122 { 8, 0x01E4 }, /* R8 - Clocking2 */
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da2xx.xml11 <value name="DITHER_PIXEL" value="0"/>
16 <value name="COLORX_4_4_4_4" value="0"/>
34 <value name="FMT_1_REVERSE" value="0"/>
91 <value name="POSITION_1_VECTOR" value="0"/>
102 <value name="CENTROIDS_ONLY" value="0"/>
108 <value name="DXCLIP_OPENGL" value="0"/>
113 <value name="POLY_DISABLED" value="0"/>
118 <value name="EDRAM_NOP" value="0"/>
125 <value name="LITTLE" value="0"/>
130 <value name="NEVER" value="0"/>
[all …]
/linux/drivers/nvme/host/
H A Dpci.c91 "this size. Use 0 to disable SGLs.");
111 if (ret != 0 || n > blk_mq_num_possible_queues(0)) in io_queue_count_set()
241 #define NVMEQ_ENABLED 0
255 IOD_ABORTED = 1U << 0,
310 memset(dev->dbbuf_dbs, 0, mem_size); in nvme_dbbuf_dma_alloc()
311 memset(dev->dbbuf_eis, 0, mem_size); in nvme_dbbuf_dma_alloc()
386 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { in nvme_dbbuf_set()
443 NVME_CTRL_PAGE_SIZE, NVME_CTRL_PAGE_SIZE, 0, numa_node); in nvme_setup_descriptor_pools()
451 NVME_SMALL_POOL_SIZE, small_align, 0, numa_node); in nvme_setup_descriptor_pools()
465 for (i = 0; i < nr_node_ids; i++) { in nvme_release_descriptor_pools()
[all …]
/linux/fs/hfsplus/
H A Dtables.c24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/linux/drivers/pci/
H A Dquirks.c92 * Return 0 if the link has been successfully retrained. Return an error
98 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ in pcie_failed_link_retrain()
268 u8 cls = 0; in pci_apply_final_quirks()
302 return 0; in pci_apply_final_quirks()
340 pci_read_config_byte(d, 0x82, &dlc); in quirk_passive_release()
344 pci_write_config_byte(d, 0x82, dlc); in quirk_passive_release()
390 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
391 pmbase = pmbase & 0xff80; in quirk_tigerpoint_bm_sts()
394 if (pm1a & 0x10) { in quirk_tigerpoint_bm_sts()
396 outw(0x10, pmbase); in quirk_tigerpoint_bm_sts()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_2_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_3_0_0_offset.h8 // base address: 0x0
9 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
10 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
11 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
12 …VGA_MEM_READ_PAGE_ADDR 0x0001
13 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
14 …VGA_RENDER_CONTROL 0x0000
16 …VGA_SEQUENCER_RESET_CONTROL 0x0001
18 …VGA_MODE_CONTROL 0x0002
20 …VGA_SURFACE_PITCH_SELECT 0x0003
[all …]
H A Ddcn_2_0_0_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]