/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/ |
H A D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/freebsd/sys/i386/i386/ |
H A D | initcpu.c | 73 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 76 * 0: keep enable CLFLUSH 98 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ in init_bluelightning() 100 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ in init_bluelightning() 102 /* Enables 13MB and 0-640KB cache. */ in init_bluelightning() 103 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); in init_bluelightning() 105 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ in init_bluelightning() 107 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ in init_bluelightning() 111 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ in init_bluelightning() 151 write_cyrix_reg(0, 0); /* dummy write */ in init_486dlc() [all …]
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/ |
H A D | eeprom.h | 9 MT_EE_CHIP_ID = 0x000, 10 MT_EE_VERSION = 0x002, 11 MT_EE_MAC_ADDR = 0x004, 12 MT_EE_NIC_CONF_0 = 0x034, 13 MT_EE_NIC_CONF_1 = 0x036, 14 MT_EE_NIC_CONF_2 = 0x042, 16 MT_EE_XTAL_TRIM_1 = 0x03a, 18 MT_EE_RSSI_OFFSET_2G = 0x046, 19 MT_EE_WIFI_RF_SETTING = 0x048, 20 MT_EE_RSSI_OFFSET_5G = 0x04a, [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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H A D | imx51-pinfunc.h | 13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 [all …]
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H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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H A D | imx53-pinfunc.h | 13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 [all …]
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H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | fsl,imxrt1050.yaml | 72 reg = <0x401f8000 0x4000>; 76 <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>, 77 <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/ |
H A D | stingray-pinctrl.dtsi | 37 reg = <0x00140000 0x250>; 45 reg = <0x0014029c 0x26c>; 47 #size-cells = <0>; 49 pinctrl-single,function-mask = <0xf>; 51 &range 0 91 MODE_GPIO 61 0x038 MODE_NITRO /* tsio_0 */ 62 0x03c MODE_NITRO /* tsio_1 */ 68 0x0ac MODE_PNOR /* nand_ce1_n */ 69 0x0b0 MODE_PNOR /* nand_ce0_n */ 70 0x0b4 MODE_PNOR /* nand_we_n */ [all …]
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/freebsd/share/man/man4/man4.i386/ |
H A D | npx.4 | 40 .Cd hint.npx.0.at="nexus" 41 .Cd hint.npx.0.port="0x0F0" 42 .Cd hint.npx.0.flags="0x0" 43 .Cd hint.npx.0.irq="13" 67 .It 0x01 69 .It 0x02 71 .It 0x04
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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/freebsd/sys/contrib/dev/mediatek/mt76/ |
H A D | mt76x02_eeprom.h | 13 MT_EE_CHIP_ID = 0x000, 14 MT_EE_VERSION = 0x002, 15 MT_EE_MAC_ADDR = 0x004, 16 MT_EE_PCI_ID = 0x00A, 17 MT_EE_ANTENNA = 0x022, 18 MT_EE_CFG1_INIT = 0x024, 19 MT_EE_NIC_CONF_0 = 0x034, 20 MT_EE_NIC_CONF_1 = 0x036, 21 MT_EE_COUNTRY_REGION_5GHZ = 0x038, 22 MT_EE_COUNTRY_REGION_2GHZ = 0x039, [all …]
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/freebsd/sys/arm/ti/ |
H A D | ti_adcreg.h | 30 #define ADC_REVISION 0x000 31 #define ADC_REV_SCHEME_MSK 0xc0000000 33 #define ADC_REV_FUNC_MSK 0x0fff0000 35 #define ADC_REV_RTL_MSK 0x0000f800 37 #define ADC_REV_MAJOR_MSK 0x00000700 39 #define ADC_REV_CUSTOM_MSK 0x000000c0 41 #define ADC_REV_MINOR_MSK 0x0000003f 42 #define ADC_SYSCFG 0x010 43 #define ADC_SYSCFG_IDLE_MSK 0x000000c0 45 #define ADC_IRQSTATUS_RAW 0x024 [all …]
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/freebsd/sys/contrib/device-tree/src/arm/hisilicon/ |
H A D | hi3620-hi4511.dts | 22 reg = <0x40000000 0x20000000>; 32 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 39 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 46 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 53 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 60 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 67 pinctrl-0 = <&board_pmx_pins>; 71 0x008 0x0 /* GPIO -- eFUSE_DOUT */ 72 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ 77 0x0f0 0x0 [all …]
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/freebsd/sys/powerpc/mpc85xx/ |
H A D | lbc.h | 36 #define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */ 37 #define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */ 38 #define LBC85XX_MAR 0x068 /* UPM address register */ 39 #define LBC85XX_MAMR 0x070 /* UPMA mode register */ 40 #define LBC85XX_MBMR 0x074 /* UPMB mode register */ 41 #define LBC85XX_MCMR 0x078 /* UPMC mode register */ 42 #define LBC85XX_MRTPR 0x084 /* Memory refresh timer prescaler */ 43 #define LBC85XX_MDR 0x088 /* UPM data register */ 44 #define LBC85XX_LSOR 0x090 /* Special operation initiation */ 45 #define LBC85XX_LURT 0x0a0 /* UPM refresh timer */ [all …]
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/freebsd/sys/arm/freescale/imx/ |
H A D | imx6_anatopreg.h | 32 #define IMX6_ANALOG_CCM_PLL_ARM 0x000 33 #define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004 34 #define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008 35 #define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C 36 #define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F 39 #define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16) 40 #define IMX6_ANALOG_CCM_PLL_USB1 0x010 41 #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014 42 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018 43 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C [all …]
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/freebsd/sys/dev/sound/pci/ |
H A D | cs4281.h | 32 #define CS4281_PCI_ID 0x60051013 39 #define CS4281PCI_HISR 0x000 40 # define CS4281PCI_HISR_DMAI 0x00040000 41 # define CS4281PCI_HISR_DMA(x) (0x0100 << (x)) 43 #define CS4281PCI_HICR 0x008 44 # define CS4281PCI_HICR_EOI 0x00000003 46 #define CS4281PCI_HIMR 0x00c 47 # define CS4281PCI_HIMR_DMAI 0x00040000 48 # define CS4281PCI_HIMR_DMA(x) (0x0100 << (x)) 50 #define CS4281PCI_IIER 0x010 [all …]
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/freebsd/sys/sys/ |
H A D | devicestat.h | 64 DEVSTAT_ALL_SUPPORTED = 0x00, 65 DEVSTAT_NO_BLOCKSIZE = 0x01, 66 DEVSTAT_NO_ORDERED_TAGS = 0x02, 67 DEVSTAT_BS_UNAVAILABLE = 0x04 71 DEVSTAT_NO_DATA = 0x00, 72 DEVSTAT_READ = 0x01, 73 DEVSTAT_WRITE = 0x02, 74 DEVSTAT_FREE = 0x03 79 DEVSTAT_TAG_SIMPLE = 0x00, 80 DEVSTAT_TAG_HEAD = 0x01, [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/ti/ |
H A D | k3-j721s2-common-proc-board.dts | 86 pinctrl-0 = <&vdd_sd_dv_pins_default>; 92 states = <1800000 0x0>, 93 <3300000 0x1>; 98 #phy-cells = <0>; 101 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 103 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; 108 #phy-cells = <0>; 111 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 117 #phy-cells = <0>; 126 #phy-cells = <0>; [all …]
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/freebsd/sys/contrib/device-tree/src/powerpc/ |
H A D | klondike.dts | 16 dcr-parent = <&{/cpus/cpu@0}>; 25 #size-cells = <0>; 27 cpu@0 { 30 reg = <0x00000000>; 44 reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */ 50 cell-index = <0>; 51 dcr-reg = <0x0c0 0x010>; 52 #address-cells = <0>; 53 #size-cells = <0>; 61 dcr-reg = <0x0d0 0x010>; [all …]
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/freebsd/sys/arm/freescale/vybrid/ |
H A D | vf_anadig.c | 55 #define ANADIG_PLL3_CTRL 0x010 /* PLL3 Control */ 56 #define ANADIG_PLL7_CTRL 0x020 /* PLL7 Control */ 57 #define ANADIG_PLL2_CTRL 0x030 /* PLL2 Control */ 58 #define ANADIG_PLL2_SS 0x040 /* PLL2 Spread Spectrum */ 59 #define ANADIG_PLL2_NUM 0x050 /* PLL2 Numerator */ 60 #define ANADIG_PLL2_DENOM 0x060 /* PLL2 Denominator */ 61 #define ANADIG_PLL4_CTRL 0x070 /* PLL4 Control */ 62 #define ANADIG_PLL4_NUM 0x080 /* PLL4 Numerator */ 63 #define ANADIG_PLL4_DENOM 0x090 /* PLL4 Denominator */ 64 #define ANADIG_PLL6_CTRL 0x0A0 /* PLL6 Control */ [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCExpr.h | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 30 VK_ABS = 0x001, 31 VK_SABS = 0x002, 32 VK_PREL = 0x003, 33 VK_GOT = 0x004, 34 VK_DTPREL = 0x005, 35 VK_GOTTPREL = 0x006, 36 VK_TPREL = 0x007, 37 VK_TLSDESC = 0x008, 38 VK_SECREL = 0x009, [all …]
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/freebsd/cddl/lib/libdtrace/ |
H A D | io.d | 45 dev_instance = 0; 72 b_blkno = 0; 73 b_lblkno = 0; 75 b_bufsize = 0; /* XXX gnn */ 86 inline int O_ACCMODE = 0x0003; 89 inline int O_RDONLY = 0x0000; 91 inline int O_WRONLY = 0x0001; 93 inline int O_RDWR = 0x0002; 96 inline int O_APPEND = 0x0008; 98 inline int O_CREAT = 0x0200; [all …]
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