/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/ |
H A D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
|
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
|
H A D | imx51-pinfunc.h | 13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 [all …]
|
H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
|
H A D | imx53-pinfunc.h | 13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 [all …]
|
H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
|
H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
|
H A D | imx6dl-pinfunc.h | 13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 [all …]
|
H A D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | fsl,imxrt1050.yaml | 72 reg = <0x401f8000 0x4000>; 76 <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>, 77 <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;
|
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/ |
H A D | stingray-pinctrl.dtsi | 37 reg = <0x00140000 0x250>; 45 reg = <0x0014029c 0x26c>; 47 #size-cells = <0>; 49 pinctrl-single,function-mask = <0xf>; 51 &range 0 91 MODE_GPIO 61 0x038 MODE_NITRO /* tsio_0 */ 62 0x03c MODE_NITRO /* tsio_1 */ 68 0x0ac MODE_PNOR /* nand_ce1_n */ 69 0x0b0 MODE_PNOR /* nand_ce0_n */ 70 0x0b4 MODE_PNOR /* nand_we_n */ [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
|
H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
|
H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
|
H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
|
/freebsd/sys/powerpc/mpc85xx/ |
H A D | lbc.h | 36 #define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */ 37 #define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */ 38 #define LBC85XX_MAR 0x068 /* UPM address register */ 39 #define LBC85XX_MAMR 0x070 /* UPMA mode register */ 40 #define LBC85XX_MBMR 0x074 /* UPMB mode register */ 41 #define LBC85XX_MCMR 0x078 /* UPMC mode register */ 42 #define LBC85XX_MRTPR 0x084 /* Memory refresh timer prescaler */ 43 #define LBC85XX_MDR 0x088 /* UPM data register */ 44 #define LBC85XX_LSOR 0x090 /* Special operation initiation */ 45 #define LBC85XX_LURT 0x0a0 /* UPM refresh timer */ [all …]
|
/freebsd/sys/arm/freescale/imx/ |
H A D | imx6_anatopreg.h | 32 #define IMX6_ANALOG_CCM_PLL_ARM 0x000 33 #define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004 34 #define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008 35 #define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C 36 #define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F 39 #define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16) 40 #define IMX6_ANALOG_CCM_PLL_USB1 0x010 41 #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014 42 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018 43 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C [all …]
|
/freebsd/sys/powerpc/powermac/ |
H A D | nvbl.c | 42 #define PCI_VENDOR_ID_NVIDIA 0x10de 44 #define NVIDIA_BRIGHT_MIN (0x0ec) 45 #define NVIDIA_BRIGHT_MAX (0x538) 47 /* nVidia's MMIO registers are at PCI BAR[0] */ 48 #define NVIDIA_MMIO_PMC (0x0) 49 #define NVIDIA_PMC_OFF (NVIDIA_MMIO_PMC + 0x10f0) 70 {0, 0}, 79 DRIVER_MODULE(nvbl, vgapci, nvbl_driver, 0, [all...] |
/freebsd/sys/contrib/device-tree/src/arm64/ti/ |
H A D | k3-j721s2-common-proc-board.dts | 86 pinctrl-0 = <&vdd_sd_dv_pins_default>; 92 states = <1800000 0x0>, 93 <3300000 0x1>; 98 #phy-cells = <0>; 101 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 103 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; 108 #phy-cells = <0>; 111 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 117 #phy-cells = <0>; 126 #phy-cells = <0>; [all …]
|
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | omap4-duovero.dtsi | 19 reg = <0x80000000 0x40000000>; /* 1 GB */ 44 #phy-cells = <0>; 47 pinctrl-0 = <&hsusb1phy_pins>; 57 pinctrl-0 = <&w2cbw0015_pins>; 71 pinctrl-0 = < 78 OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ 79 OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ 85 OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ 86 OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ 87 OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ [all …]
|
H A D | omap4-var-som-om44.dtsi | 15 reg = <0x80000000 0x40000000>; /* 1 GB */ 38 pinctrl-0 = < 45 #phy-cells = <0>; 64 pinctrl-0 = < 70 OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ 71 OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ 77 OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ 78 OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ 84 OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ 85 OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
H A D | hikey960-pinctrl.dtsi | 18 reg = <0x0 0xe896c000 0x0 0x1f0>; 20 #gpio-range-cells = <0x3>; 21 pinctrl-single,register-width = <0x20>; 22 pinctrl-single,function-mask = <0x7>; 25 &range 0 7 0 26 &range 8 116 0>; 30 0x008 MUX_M1 /* PMU1_SSI */ 31 0x00c MUX_M1 /* PMU2_SSI */ 32 0x010 MUX_M1 /* PMU_CLKOUT */ 33 0x100 MUX_M1 /* PMU_HKADC_SSI */ [all …]
|
/freebsd/sys/arm/nvidia/tegra124/ |
H A D | tegra124_car.h | 38 #define RST_DEVICES_L 0x004 39 #define RST_DEVICES_H 0x008 40 #define RST_DEVICES_U 0x00C 41 #define CLK_OUT_ENB_L 0x010 42 #define CLK_OUT_ENB_H 0x014 43 #define CLK_OUT_ENB_U 0x018 44 #define CCLK_BURST_POLICY 0x020 45 #define SUPER_CCLK_DIVIDER 0x024 46 #define SCLK_BURST_POLICY 0x028 47 #define SUPER_SCLK_DIVIDER 0x02c [all …]
|
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/ |
H A D | hi3620-hi4511.dts | 22 reg = <0x40000000 0x20000000>; 32 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 39 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 46 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 53 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 60 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 67 pinctrl-0 = <&board_pmx_pins>; 71 0x008 0x0 /* GPIO -- eFUSE_DOUT */ 72 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ 77 0x0f0 0x0 [all …]
|
/freebsd/sys/arm/freescale/vybrid/ |
H A D | vf_iomuxc.h | 29 #define IOMUXC(n) (n * 0x04) 31 #define IOMUXC_PTA6 0x000 /* Software MUX Pad Control Register 0 */ 32 #define IOMUXC_PTA8 0x004 /* Software MUX Pad Control Register 1 */ 33 #define IOMUXC_PTA9 0x008 /* Software MUX Pad Control Register 2 */ 34 #define IOMUXC_PTA10 0x00C /* Software MUX Pad Control Register 3 */ 35 #define IOMUXC_PTA11 0x010 /* Software MUX Pad Control Register 4 */ 36 #define IOMUXC_PTA12 0x014 /* Software MUX Pad Control Register 5 */ 37 #define IOMUXC_PTA16 0x018 /* Software MUX Pad Control Register 6 */ 38 #define IOMUXC_PTA17 0x01C /* Software MUX Pad Control Register 7 */ 39 #define IOMUXC_PTA18 0x020 /* Software MUX Pad Control Register 8 */ [all …]
|