Searched +full:0 +full:x08a00000 (Results 1 – 6 of 6) sorted by relevance
84 reg = <0x08a00000 0x10000>;
30 - pinctrl-0 : phandle referencing pin configuration for this tsin configuration36 - tsin-num : tsin id of the InputBlock (must be between 0 to 6)55 reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;59 pinctrl-0 = <&pinctrl_tsin0_serial>;73 tsin0: port@0 {74 tsin-num = <0>;
28 #size-cells = <0>;30 simple-audio-card,dai-link@0 {31 reg = <0>;69 sound-dai = <&sti_sasg_codec 0>;101 st,i2c-min-scl-pulse-width-us = <0>;108 st,i2c-min-scl-pulse-width-us = <0>;138 st,i2c-min-scl-pulse-width-us = <0>;150 fixed-link = <0 1 1000 0 0>;156 reg = <0x08a20000 0x10000>,157 <0x08a00000 0x4000>;[all …]
23 #clock-cells = <0>;29 #clock-cells = <0>;35 #size-cells = <0>;37 cpu0: cpu@0 {40 reg = <0x0>;54 reg = <0x1>;67 reg = <0x2>;80 reg = <0x3>;99 qcom,dload-mode = <&tcsr 0x6100>;111 opp-supported-hw = <0xf>;[all …]
26 #define mmSDMA0_DEC_START_DEFAULT 0x0000000027 #define mmSDMA0_PG_CNTL_DEFAULT 0x0000000028 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x0000000029 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x0000000030 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x0000000031 #define mmSDMA0_POWER_CNTL_DEFAULT 0x4000005032 #define mmSDMA0_CLK_CTRL_DEFAULT 0x0000010033 #define mmSDMA0_CNTL_DEFAULT 0x000000c234 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af010735 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044[all …]
27 #define mmSDMA0_DEC_START_DEFAULT 0x0000000028 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x0000000029 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x0000000030 #define mmSDMA0_PG_CNTL_DEFAULT 0x0000000031 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x0000000032 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x0000000033 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x0000000034 #define mmSDMA0_POWER_CNTL_DEFAULT 0x4000005035 #define mmSDMA0_CLK_CTRL_DEFAULT 0x0000010036 #define mmSDMA0_CNTL_DEFAULT 0x000000c2[all …]