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Searched +full:0 +full:x08a00000 (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,glink-edge.yaml84 reg = <0x08a00000 0x10000>;
/linux/Documentation/devicetree/bindings/media/
H A Dstih407-c8sectpfe.txt30 - pinctrl-0 : phandle referencing pin configuration for this tsin configuration
36 - tsin-num : tsin id of the InputBlock (must be between 0 to 6)
55 reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
59 pinctrl-0 = <&pinctrl_tsin0_serial>;
73 tsin0: port@0 {
74 tsin-num = <0>;
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]