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/linux/arch/mips/alchemy/common/
H A Dsleeper.S46 sw k0, 0x20(sp)
48 sw k0, 0x1c(sp)
50 sw k0, 0x18(sp)
52 sw k0, 0x14(sp)
56 lw t0, 0(t1)
65 lui t3, 0xb190 /* sys_xxx */
66 sw sp, 0x0018(t3)
68 sw k0, 0x001c(t3)
73 sw zero, 0x0078(t3) /* sys_slppwr */
75 sw zero, 0x007c(t3) /* sys_sleep */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_0_offset.h25 #define mmUMCCH0_0_EccCtrl 0x0053
26 #define mmUMCCH0_0_EccCtrl_BASE_IDX 0
27 #define mmUMCCH1_0_EccCtrl 0x0853
28 #define mmUMCCH1_0_EccCtrl_BASE_IDX 0
29 #define mmUMCCH2_0_EccCtrl 0x1053
30 #define mmUMCCH2_0_EccCtrl_BASE_IDX 0
31 #define mmUMCCH3_0_EccCtrl 0x1853
32 #define mmUMCCH3_0_EccCtrl_BASE_IDX 0
34 #define mmUMCCH0_0_UMC_CONFIG 0x0040
35 #define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0
[all …]
/linux/arch/arm/mach-imx/
H A Diim.h11 #define MXC_IIMSTAT 0x0000
12 #define MXC_IIMSTATM 0x0004
13 #define MXC_IIMERR 0x0008
14 #define MXC_IIMEMASK 0x000C
15 #define MXC_IIMFCTL 0x0010
16 #define MXC_IIMUA 0x0014
17 #define MXC_IIMLA 0x0018
18 #define MXC_IIMSDAT 0x001C
19 #define MXC_IIMPREV 0x0020
20 #define MXC_IIMSREV 0x0024
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x0070>;
18 #clock-cells = <0>;
22 reg = <0x0070>;
26 #clock-cells = <0>;
32 #clock-cells = <0>;
37 reg = <0x0070>;
42 #clock-cells = <0>;
46 reg = <0x0810>;
50 #clock-cells = <0>;
[all …]
H A Domap2430-clocks.dtsi10 #clock-cells = <0>;
13 reg = <0x78>;
17 #clock-cells = <0>;
23 #clock-cells = <0>;
27 reg = <0x78>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
41 reg = <0x78>;
45 #clock-cells = <0>;
53 #clock-cells = <0>;
[all …]
/linux/lib/crc/
H A Dcrc-ccitt.c11 * be seen in entry 128, 0x8408. This corresponds to x^0 + x^5 + x^12.
15 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
16 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
17 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
18 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
19 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
20 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
21 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
22 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
23 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
[all …]
H A Dcrc-itu-t.c11 /* CRC table for the CRC ITU-T V.41 0x1021 (x^16 + x^12 + x^5 + 1) */
13 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
14 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
15 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
16 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
17 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
18 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
19 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
20 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
21 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
[all …]
/linux/drivers/net/ethernet/engleder/
H A Dtsnep_hw.h12 #define ECM_TYPE 0x0000
13 #define ECM_REVISION_MASK 0x000000FF
14 #define ECM_REVISION_SHIFT 0
15 #define ECM_VERSION_MASK 0x0000FF00
17 #define ECM_QUEUE_COUNT_MASK 0x00070000
19 #define ECM_GATE_CONTROL 0x02000000
22 #define ECM_SYSTEM_TIME_LOW 0x0008
23 #define ECM_SYSTEM_TIME_HIGH 0x000C
26 #define ECM_CLOCK_RATE 0x0010
27 #define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF
[all …]
/linux/include/video/
H A Datmel_lcdc.h18 #define ATMEL_LCDC_WIRING_BGR 0
37 #define ATMEL_LCDC_DMABADDR1 0x00
38 #define ATMEL_LCDC_DMABADDR2 0x04
39 #define ATMEL_LCDC_DMAFRMPT1 0x08
40 #define ATMEL_LCDC_DMAFRMPT2 0x0c
41 #define ATMEL_LCDC_DMAFRMADD1 0x10
42 #define ATMEL_LCDC_DMAFRMADD2 0x14
44 #define ATMEL_LCDC_DMAFRMCFG 0x18
45 #define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
47 #define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
[all …]
/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil.h34 #define LTSSM_STATUS 0x0404
35 #define LTSSM_STATUS_L0_MASK 0x3f
36 #define LTSSM_STATUS_L0 0x2d
38 #define PAB_CTRL 0x0808
39 #define AMBA_PIO_ENABLE_SHIFT 0
42 #define PAGE_SEL_MASK 0x3f
43 #define PAGE_LO_MASK 0x3ff
46 #define PAB_ACTIVITY_STAT 0x81c
48 #define PAB_AXI_PIO_CTRL 0x0840
49 #define APIO_EN_MASK 0xf
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl502d.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_WAIT_FOR_IDLE 0x0110
30 …_WAIT_FOR_IDLE_V 31:0
32 …_SET_DST_CONTEXT_DMA 0x0184
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
35 …_SET_SRC_CONTEXT_DMA 0x0188
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
38 …_SET_SEMAPHORE_CONTEXT_DMA 0x018c
39 …_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
[all …]
H A Dcl902d.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_WAIT_FOR_IDLE 0x0110
31 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_FORMAT 0x0200
34 …_SET_DST_FORMAT_V 7:0
35 …_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
36 …_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
37 …_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
38 …_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-dib0700-rc5.c18 { 0x0700, KEY_MUTE },
19 { 0x0701, KEY_MENU }, /* Pinnacle logo */
20 { 0x0739, KEY_POWER },
21 { 0x0703, KEY_VOLUMEUP },
22 { 0x0709, KEY_VOLUMEDOWN },
23 { 0x0706, KEY_CHANNELUP },
24 { 0x070c, KEY_CHANNELDOWN },
25 { 0x070f, KEY_NUMERIC_1 },
26 { 0x0715, KEY_NUMERIC_2 },
27 { 0x0710, KEY_NUMERIC_3 },
[all …]
/linux/drivers/net/phy/
H A Dmarvell-88q2xxx.c15 #define PHY_ID_88Q2220_REVB0 (MARVELL_PHY_ID_88Q2220 | 0x1)
16 #define PHY_ID_88Q2220_REVB1 (MARVELL_PHY_ID_88Q2220 | 0x2)
17 #define PHY_ID_88Q2220_REVB2 (MARVELL_PHY_ID_88Q2220 | 0x3)
20 #define MDIO_MMD_AN_MV_STAT_ANEG 0x0100
21 #define MDIO_MMD_AN_MV_STAT_LOCAL_RX 0x1000
22 #define MDIO_MMD_AN_MV_STAT_REMOTE_RX 0x2000
23 #define MDIO_MMD_AN_MV_STAT_LOCAL_MASTER 0x4000
24 #define MDIO_MMD_AN_MV_STAT_MS_CONF_FAULT 0x8000
27 #define MDIO_MMD_AN_MV_STAT2_AN_RESOLVED 0x0800
28 #define MDIO_MMD_AN_MV_STAT2_100BT1 0x2000
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg84.c37 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_vsi()
39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); in g84_sor_hdmi_infoframe_vsi()
45 nvkm_wr32(device, 0x616544 + hoff, vsi.header); in g84_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low); in g84_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high); in g84_sor_hdmi_infoframe_vsi()
49 /* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */ in g84_sor_hdmi_infoframe_vsi()
50 /* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */ in g84_sor_hdmi_infoframe_vsi()
52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); in g84_sor_hdmi_infoframe_vsi()
60 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_avi()
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_infoframe_avi()
[all …]
/linux/drivers/video/fbdev/kyro/
H A DSTG4000Reg.h54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
75 /* 0h */
76 volatile u32 Thread0Enable; /* 0x0000 */
77 volatile u32 Thread1Enable; /* 0x0004 */
78 volatile u32 Thread0Recover; /* 0x0008 */
79 volatile u32 Thread1Recover; /* 0x000C */
80 volatile u32 Thread0Step; /* 0x0010 */
81 volatile u32 Thread1Step; /* 0x0014 */
[all …]
/linux/drivers/clk/renesas/
H A Dr8a779a0-cpg-mssr.c65 #define CPG_PLL20CR 0x0834 /* PLL20 Control Register */
66 #define CPG_PLL21CR 0x0838 /* PLL21 Control Register */
67 #define CPG_PLL30CR 0x083c /* PLL30 Control Register */
68 #define CPG_PLL31CR 0x0840 /* PLL31 Control Register */
69 #define CPG_PLL4CR 0x0844 /* PLL4 Control Register */
102 DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
145 DEF_MOD("3dge", 0, R8A779A0_CLK_ZG),
267 * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
268 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19
269 * 1 0 Prohibited setting
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
/linux/include/linux/mfd/
H A Dmotorola-cpcap.h17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h13 #define SXGBE_CORE_TX_CONFIG_REG 0x0000
14 #define SXGBE_CORE_RX_CONFIG_REG 0x0004
15 #define SXGBE_CORE_PKT_FILTER_REG 0x0008
16 #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
17 #define SXGBE_CORE_HASH_TABLE_REG0 0x0010
18 #define SXGBE_CORE_HASH_TABLE_REG1 0x0014
19 #define SXGBE_CORE_HASH_TABLE_REG2 0x0018
20 #define SXGBE_CORE_HASH_TABLE_REG3 0x001C
21 #define SXGBE_CORE_HASH_TABLE_REG4 0x0020
22 #define SXGBE_CORE_HASH_TABLE_REG5 0x0024
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc.h11 #define DISPC_REVISION 0x0000
12 #define DISPC_SYSCONFIG 0x0010
13 #define DISPC_SYSSTATUS 0x0014
14 #define DISPC_IRQSTATUS 0x0018
15 #define DISPC_IRQENABLE 0x001C
16 #define DISPC_CONTROL 0x0040
17 #define DISPC_CONFIG 0x0044
18 #define DISPC_CAPABLE 0x0048
19 #define DISPC_LINE_STATUS 0x005C
20 #define DISPC_LINE_NUMBER 0x0060
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddispc.h13 #define DISPC_REVISION 0x0000
14 #define DISPC_SYSCONFIG 0x0010
15 #define DISPC_SYSSTATUS 0x0014
16 #define DISPC_IRQSTATUS 0x0018
17 #define DISPC_IRQENABLE 0x001C
18 #define DISPC_CONTROL 0x0040
19 #define DISPC_CONFIG 0x0044
20 #define DISPC_CAPABLE 0x0048
21 #define DISPC_LINE_STATUS 0x005C
22 #define DISPC_LINE_NUMBER 0x0060
[all …]
/linux/drivers/resctrl/
H A Dmpam_internal.h212 COUNT_BOTH = 0,
400 #define MPAM_ARCHITECTURE_V1 0x10
404 #define MPAMF_IDR 0x0000 /* features id register */
405 #define MPAMF_IIDR 0x0018 /* implementer id register */
406 #define MPAMF_AIDR 0x0020 /* architectural id register */
407 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */
408 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */
409 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */
410 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */
411 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2059.c17 { 0x051, 0x70 }, { 0x05a, 0x03 }, { 0x079, 0x01 }, { 0x082, 0x70 },
18 { 0x083, 0x00 }, { 0x084, 0x70 }, { 0x09a, 0x7f }, { 0x0b6, 0x10 },
19 { 0x188, 0x05 },
61 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
62 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
63 0x00, 0x00, 0x00, 0xd0, 0x00),
64 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
68 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
69 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
70 0x00, 0x00, 0x00, 0xd0, 0x00),
[all …]
/linux/include/uapi/linux/
H A Dzorro_ids.h9 #define ZORRO_MANUF_PACIFIC_PERIPHERALS 0x00D3
10 #define ZORRO_PROD_PACIFIC_PERIPHERALS_SE_2000_A500 ZORRO_ID(PACIFIC_PERIPHERALS, 0x00, 0)
11 #define ZORRO_PROD_PACIFIC_PERIPHERALS_SCSI ZORRO_ID(PACIFIC_PERIPHERALS, 0x0A, 0)
13 #define ZORRO_MANUF_MACROSYSTEMS_USA_2 0x0100
14 #define ZORRO_PROD_MACROSYSTEMS_WARP_ENGINE ZORRO_ID(MACROSYSTEMS_USA_2, 0x13, 0)
16 #define ZORRO_MANUF_KUPKE_1 0x00DD
17 #define ZORRO_PROD_KUPKE_GOLEM_RAM_BOX_2MB ZORRO_ID(KUPKE_1, 0x00, 0)
19 #define ZORRO_MANUF_MEMPHIS 0x0100
20 #define ZORRO_PROD_MEMPHIS_STORMBRINGER ZORRO_ID(MEMPHIS, 0x00, 0)
22 #define ZORRO_MANUF_3_STATE 0x0200
[all …]

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