Searched +full:0 +full:x08340000 (Results 1 – 4 of 4) sorted by relevance
58 Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in81 0x0 - MC portals82 0x1 - QBMAN portals140 const: 0161 reg = <0x0c000000 0x40>, /* MC portal base */162 <0x08340000 0x40000>; /* MC control reg */164 * Region type 0x0 - MC portals165 * Region type 0x1 - QBMAN portals167 ranges = <0x0 0x0 0x8 0x0c000000 0x4000000168 0x1 0x0 0x8 0x18000000 0x8000000>;[all …]
27 #size-cells = <0>;30 cpu0: cpu@0 {33 reg = <0x0>;34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;42 reg = <0x1>;43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;51 reg = <0x2>;52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;60 reg = <0x3>;61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;[all …]
33 #size-cells = <0>;38 reg = <0x00000000 0x80000000 0 0x80000000>;44 #clock-cells = <0>;51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */67 reg = <0x0 0x6020000 0 0x20000>;73 reg = <0x0 0x1e60000 0x0 0x4>;[all …]
12 /memreserve/ 0x80000000 0x00010000;26 #size-cells = <0>;29 cpu0: cpu@0 {33 reg = <0x0>;34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;35 d-cache-size = <0x8000>;38 i-cache-size = <0xC000>;50 reg = <0x1>;51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;52 d-cache-size = <0x8000>;[all …]