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/linux/sound/pci/oxygen/
H A Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
H A Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/linux/sound/soc/codecs/
H A Dssm2602.h33 #define SSM2602_LINVOL 0x00
34 #define SSM2602_RINVOL 0x01
35 #define SSM2602_LOUT1V 0x02
36 #define SSM2602_ROUT1V 0x03
37 #define SSM2602_APANA 0x04
38 #define SSM2602_APDIGI 0x05
39 #define SSM2602_PWR 0x06
40 #define SSM2602_IFACE 0x07
41 #define SSM2602_SRATE 0x08
42 #define SSM2602_ACTIVE 0x09
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
H A Dpinctrl-mt8365.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0x710, 0, 2),
29 MTK_PIN_DRV_GRP(1, 0x710, 0, 2),
30 MTK_PIN_DRV_GRP(2, 0x710, 0, 2),
31 MTK_PIN_DRV_GRP(3, 0x710, 0, 2),
32 MTK_PIN_DRV_GRP(4, 0x710, 4, 2),
33 MTK_PIN_DRV_GRP(5, 0x710, 4, 2),
34 MTK_PIN_DRV_GRP(6, 0x710, 4, 2),
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
43 #define S5P_PIN_PULL_DISABLE 0
86 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
106 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
107 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
108 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
109 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
110 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
[all …]
/linux/drivers/net/ethernet/seeq/
H A Dsgiseeq.h35 #define SEEQ_RSTAT_OVERF 0x001 /* Overflow */
36 #define SEEQ_RSTAT_CERROR 0x002 /* CRC error */
37 #define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */
38 #define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */
39 #define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */
40 #define SEEQ_RSTAT_FIG 0x020 /* Frame is good */
41 #define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */
42 #define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */
43 #define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */
44 #define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */
[all …]
/linux/arch/mips/mm/
H A Dc-r3k.c40 *p = 0xa5a55a5a; in r3k_cache_size()
44 if (dummy != 0xa5a55a5a || (status & ST0_CM)) { in r3k_cache_size()
45 size = 0; in r3k_cache_size()
47 for (size = 128; size <= 0x40000; size <<= 1) in r3k_cache_size()
48 *(p + size) = 0; in r3k_cache_size()
51 (size <= 0x40000) && (*(p + size) == 0); in r3k_cache_size()
54 if (size > 0x40000) in r3k_cache_size()
55 size = 0; in r3k_cache_size()
75 for (i = 0; i < 128; i++) in r3k_cache_lsize()
76 *(p + i) = 0; in r3k_cache_lsize()
[all …]
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq6h-pins.dtsi9 * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func
14 * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU
27 0x000 0x200 // I2C0_SCL pin
28 0x004 0x200 // I2C0_SDA pin
33 0x008 0x200 // I2C1_SCL pin
34 0x00c 0x200 // I2C1_SDA pin
39 0x080 1 // GPIO_C4__SMA0_MDC pin
40 0x084 1 // GPIO_C5__SMA0_MDIO pin
44 pinctrl-single,pins = <0x0a8 1>; // UART0 pin group
47 pinctrl-single,pins = <0x0a0 1>; // UART1 pin group
[all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Duncore-io.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
8 "PortMask": "0x000",
13 "Counter": "0,1,2,3",
14 "EventCode": "0xC2",
17 "FCMask": "0x07",
19 "PortMask": "0x0FF",
20 "UMask": "0x4",
25 "Counter": "0,1,2,3",
26 "EventCode": "0xC2",
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c176 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
178 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
180 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
182 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
185 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
187 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
H A Dclk-mt7622.c217 .set_ofs = 0x120,
218 .clr_ofs = 0x120,
219 .sta_ofs = 0x120,
223 .set_ofs = 0x128,
224 .clr_ofs = 0x128,
225 .sta_ofs = 0x128,
229 .set_ofs = 0x8,
230 .clr_ofs = 0x10,
231 .sta_ofs = 0x18,
235 .set_ofs = 0xC,
[all …]
H A Dclk-mt7988-topckgen.c107 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
108 0, 2, 7, 0x1c0, 0),
109 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
110 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
111 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
112 0x004, 0x008, 16, 2, 23, 0x1C0, 2),
113 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
114 0x004, 0x008, 24, 2, 31, 0x1C0, 3),
116 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
117 0x018, 0, 1, 7, 0x1C0, 4),
[all …]
H A Dclk-mt8516.c24 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
366 0x000, 0, 1),
368 0x000, 4, 4),
370 0x000, 11, 3),
372 0x000, 19, 1),
374 0x000, 20, 3),
376 0x000, 24, 2),
378 0x000, 26, 1),
380 0x000, 27, 3),
383 0x004, 0, 7),
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-com.h10 #define QSERDES_COM_ATB_SEL1 0x000
11 #define QSERDES_COM_ATB_SEL2 0x004
12 #define QSERDES_COM_FREQ_UPDATE 0x008
13 #define QSERDES_COM_BG_TIMER 0x00c
14 #define QSERDES_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_COM_SSC_PER1 0x01c
18 #define QSERDES_COM_SSC_PER2 0x020
19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Duncore-io.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
8 "PortMask": "0x000",
13 "Counter": "0,1,2,3",
14 "EventCode": "0xC2",
17 "FCMask": "0x07",
19 "PortMask": "0x0FF",
20 "UMask": "0x4",
25 "Counter": "0,1,2,3",
26 "EventCode": "0xC2",
[all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Duncore-io.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
8 "PortMask": "0x000",
13 "Counter": "0,1,2,3",
14 "EventCode": "0xC2",
17 "FCMask": "0x07",
19 "PortMask": "0x0FF",
20 "UMask": "0x4",
25 "Counter": "0,1,2,3",
26 "EventCode": "0xC2",
[all …]
/linux/include/linux/spi/
H A Dmxs-spi.h19 #define HW_SSP_CTRL0 0x000
27 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
33 #define BP_SSP_CTRL0_XFER_COUNT 0
34 #define BM_SSP_CTRL0_XFER_COUNT 0xffff
35 #define HW_SSP_CMD0 0x010
41 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
43 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
44 #define BP_SSP_CMD0_CMD 0
45 #define BM_SSP_CMD0_CMD 0xff
46 #define HW_SSP_CMD1 0x020
[all …]
/linux/drivers/video/fbdev/riva/
H A Driva_hw.h50 #define RIVA_SW_VERSION 0x00010003
60 #define FALSE 0
63 #define NULL 0
91 #define NV_ARCH_03 0x03
92 #define NV_ARCH_04 0x04
93 #define NV_ARCH_10 0x10
94 #define NV_ARCH_20 0x20
95 #define NV_ARCH_30 0x30
96 #define NV_ARCH_40 0x40
116 U032 reserved01[0x0BB];
[all …]
/linux/arch/sparc/lib/
H A Dbzero.S14 and %o1, 0xff, %o3
30 prefetch [%o0 + 0x000], #n_writes
31 andcc %o0, 0x3, %g0
33 1: stb %o2, [%o0 + 0x00]
35 andcc %o0, 0x3, %g0
38 2: andcc %o0, 0x7, %g0
40 stw %o2, [%o0 + 0x00]
43 3: and %o1, 0x38, %g1
44 cmp %o1, 0x40
45 andn %o1, 0x3f, %o4
[all …]
/linux/arch/arm/mach-omap1/
H A Dmmc.h7 #define OMAP1_MMC_SIZE 0x080
8 #define OMAP1_MMC1_BASE 0xfffb7800
9 #define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
/linux/arch/sh/include/mach-dreamcast/mach/
H A Dmaple.h11 MAPLE_DMA_ORDER - PAGE_SHIFT : 0)
14 #define MAPLE_BASE 0xa05f6c00
15 #define MAPLE_DMAADDR (MAPLE_BASE+0x04)
16 #define MAPLE_TRIGTYPE (MAPLE_BASE+0x10)
17 #define MAPLE_ENABLE (MAPLE_BASE+0x14)
18 #define MAPLE_STATE (MAPLE_BASE+0x18)
19 #define MAPLE_SPEED (MAPLE_BASE+0x80)
20 #define MAPLE_RESET (MAPLE_BASE+0x8c)
22 #define MAPLE_MAGIC 0x6155404f
23 #define MAPLE_2MBPS 0
[all …]

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