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/linux/drivers/mtd/maps/
H A Dscx200_docflash.c27 static int probe = 0; /* Don't autoprobe */
28 static unsigned size = 0x1000000; /* 16 MiB the whole ISA address space */
32 module_param(probe, int, 0);
34 module_param(size, int, 0);
36 module_param(width, int, 0);
38 module_param(flashtype, charp, 0);
51 .offset = 0,
52 .size = 0xc0000
56 .offset = 0xc0000,
57 .size = 0x40000
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-db8500.dtsi8 operating-points = <998400 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
H A Dste-db8520.dtsi8 operating-points = <1152000 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
/linux/arch/powerpc/include/asm/
H A Dreg_8xx.h29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
[all …]
H A Dcpm2.h20 #define CPM_CR_RST ((uint)0x80000000)
21 #define CPM_CR_PAGE ((uint)0x7c000000)
22 #define CPM_CR_SBLOCK ((uint)0x03e00000)
23 #define CPM_CR_FLG ((uint)0x00010000)
24 #define CPM_CR_MCN ((uint)0x00003fc0)
25 #define CPM_CR_OPCODE ((uint)0x0000000f)
29 #define CPM_CR_SCC1_SBLOCK (0x04)
30 #define CPM_CR_SCC2_SBLOCK (0x05)
31 #define CPM_CR_SCC3_SBLOCK (0x06)
32 #define CPM_CR_SCC4_SBLOCK (0x07)
[all …]
/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-wpcm450-supermicro-x9sci-ln4f.dts7 /memreserve/ 0x07000000 0x01000000;
27 memory@0 {
29 reg = <0 0x08000000>; /* 128 MiB */
35 pinctrl-0 = <&key_pins>;
47 pinctrl-0 = <&led_pins>;
64 flash@0 {
65 reg = <0>;
72 /* 0 */ "", "host-reset-control-n", "", "", "", "", "", "",
78 /* 0 */ "", "", "", "", "led-heartbeat", "", "", "led-uid",
84 /* 0 */ "", "", "", "", "", "", "", "",
/linux/drivers/net/wireless/silabs/wfx/
H A Dhwio.h33 #define CFG_ERR_SPI_FRAME 0x00000001 /* only with SPI */
34 #define CFG_ERR_SDIO_BUF_MISMATCH 0x00000001 /* only with SDIO */
35 #define CFG_ERR_BUF_UNDERRUN 0x00000002
36 #define CFG_ERR_DATA_IN_TOO_LARGE 0x00000004
37 #define CFG_ERR_HOST_NO_OUT_QUEUE 0x00000008
38 #define CFG_ERR_BUF_OVERRUN 0x00000010
39 #define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
40 #define CFG_ERR_HOST_NO_IN_QUEUE 0x00000040
41 #define CFG_ERR_HOST_CRC_MISS 0x00000080 /* only with SDIO */
42 #define CFG_SPI_IGNORE_CS 0x00000080 /* only with SPI */
[all …]
/linux/drivers/scsi/mpi3mr/mpi/
H A Dmpi30_init.h38 #define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID (0x80)
39 #define MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE (0x40)
40 #define MPI3_SCSIIO_FLAGS_LARGE_CDB (0x60000000)
41 #define MPI3_SCSIIO_FLAGS_LARGE_CDB_MASK (0x60000000)
43 #define MPI3_SCSIIO_FLAGS_IOC_USE_ONLY_27_MASK (0x18000000)
45 #define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000)
46 #define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000)
47 #define MPI3_SCSIIO_FLAGS_CDB_IN_SEPARATE_BUFFER (0x40000000)
48 #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_MASK (0x07000000)
50 #define MPI3_SCSIIO_FLAGS_DATADIRECTION_MASK (0x000c0000)
[all …]
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k1000-ref.dts25 reg = <0x0 0x00200000 0x0 0x06e00000>,
26 <0x0 0x08000000 0x0 0x07000000>,
27 <0x0 0x90000000 0x1 0xe0000000>;
38 size = <0x0 0x2000000>;
46 pwms = <&pwm1 0 100000 0>;
58 pinctrl-0 = <&sdio_pins_default>;
72 #size-cells = <0>;
73 phy0: ethernet-phy@0 {
74 reg = <0>;
87 #size-cells = <0>;
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/linux/include/linux/bcma/
H A Dbcma_regs.h7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
/linux/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/linux/drivers/video/fbdev/
H A Di740_reg.h37 #define XRX 0x3D6
38 #define MRX 0x3D2
41 #define DACMASK 0x3C6
42 #define DACSTATE 0x3C7
43 #define DACRX 0x3C7
44 #define DACWX 0x3C8
45 #define DACDATA 0x3C9
48 #define START_ADDR_HI 0x0C
49 #define START_ADDR_LO 0x0D
50 #define VERT_SYNC_END 0x11
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
/linux/arch/m68k/include/asm/
H A Dm54xxpci.h21 #define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
22 #define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
23 #define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
24 #define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
25 #define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
26 #define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
27 #define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
28 #define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
29 #define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
30 #define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
[all …]
/linux/arch/microblaze/include/asm/
H A Dpvr.h13 #define PVR_MSR_BIT 0x400
22 #define PVR0_PVR_FULL_MASK 0x80000000
23 #define PVR0_USE_BARREL_MASK 0x40000000
24 #define PVR0_USE_DIV_MASK 0x20000000
25 #define PVR0_USE_HW_MUL_MASK 0x10000000
26 #define PVR0_USE_FPU_MASK 0x08000000
27 #define PVR0_USE_EXC_MASK 0x04000000
28 #define PVR0_USE_ICACHE_MASK 0x02000000
29 #define PVR0_USE_DCACHE_MASK 0x01000000
30 #define PVR0_USE_MMU 0x00800000
[all …]
/linux/drivers/mtd/devices/
H A Dms02-nv.c26 "ms02-nv.c: v.1.0.0 13 Aug 2001 Maciej W. Rozycki.\n";
35 * at any 8MiB boundary within a 0MiB up to 112MiB range or at any 32MiB
36 * boundary within a 0MiB up to 448MiB range. We don't support a module
37 * at 0MiB, though.
40 0x07000000, 0x06800000, 0x06000000, 0x05800000, 0x05000000,
41 0x04800000, 0x04000000, 0x03800000, 0x03000000, 0x02800000,
42 0x02000000, 0x01800000, 0x01000000, 0x00800000
60 return 0; in ms02nv_read()
70 return 0; in ms02nv_write()
92 return 0; in ms02nv_probe_one()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_mci.h20 #define MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
25 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
29 #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
32 MCI_GPM_COEX_QUERY_BT_ALL_INFO = BIT(0),
50 #define MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
51 #define MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
52 #define MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
53 #define MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
54 #define MCI_BT_MCI_FLAGS_DEBUG 0x00000020
55 #define MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt73usb.h20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
[all …]
/linux/sound/pci/oxygen/
H A Doxygen_regs.h6 #define OXYGEN_DMA_A_ADDRESS 0x00 /* 32-bit base address */
7 #define OXYGEN_DMA_A_COUNT 0x04 /* buffer counter (dwords) */
8 #define OXYGEN_DMA_A_TCOUNT 0x06 /* interrupt counter (dwords) */
11 #define OXYGEN_DMA_B_ADDRESS 0x08
12 #define OXYGEN_DMA_B_COUNT 0x0c
13 #define OXYGEN_DMA_B_TCOUNT 0x0e
16 #define OXYGEN_DMA_C_ADDRESS 0x10
17 #define OXYGEN_DMA_C_COUNT 0x14
18 #define OXYGEN_DMA_C_TCOUNT 0x16
21 #define OXYGEN_DMA_SPDIF_ADDRESS 0x18
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dfec_mpc52xx.h34 u32 fec_id; /* FEC + 0x000 */
35 u32 ievent; /* FEC + 0x004 */
36 u32 imask; /* FEC + 0x008 */
38 u32 reserved0[1]; /* FEC + 0x00C */
39 u32 r_des_active; /* FEC + 0x010 */
40 u32 x_des_active; /* FEC + 0x014 */
41 u32 r_des_active_cl; /* FEC + 0x018 */
42 u32 x_des_active_cl; /* FEC + 0x01C */
43 u32 ivent_set; /* FEC + 0x020 */
44 u32 ecntrl; /* FEC + 0x024 */
[all …]
/linux/drivers/spi/
H A Dspi-falcon.c19 #define FALCON_SPI_XFER_BEGIN (1 << 0)
23 #define BUSRCON0 0x00000010
25 #define BUSWCON0 0x00000018
27 #define SFCON 0x00000080
29 #define SFTIME 0x00000084
31 #define SFSTAT 0x00000088
33 #define SFCMD 0x0000008C
35 #define SFADDR 0x00000090
37 #define SFDATA 0x00000094
39 #define SFIO 0x00000098
[all …]
/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h19 #define AR71XX_APB_BASE 0x18000000
20 #define AR71XX_GE0_BASE 0x19000000
21 #define AR71XX_GE0_SIZE 0x10000
22 #define AR71XX_GE1_BASE 0x1a000000
23 #define AR71XX_GE1_SIZE 0x10000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/linux/arch/mips/ath25/
H A Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/linux/drivers/media/usb/gspca/
H A Dstk014.c37 .priv = 0},
47 if (gspca_dev->usb_err < 0) in reg_r()
48 return 0; in reg_r()
49 ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), in reg_r()
50 0x00, in reg_r()
52 0x00, in reg_r()
56 if (ret < 0) { in reg_r()
59 return 0; in reg_r()
61 return gspca_dev->usb_buf[0]; in reg_r()
71 if (gspca_dev->usb_err < 0) in reg_w()
[all …]

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