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/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
H A Dclk-exynosautov9.c32 /* Register Offset definitions for CMU_TOP (0x1b240000) */
33 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
34 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
35 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
36 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
37 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
38 #define PLL_CON0_PLL_SHARED0 0x0100
39 #define PLL_CON3_PLL_SHARED0 0x010c
40 #define PLL_CON0_PLL_SHARED1 0x0140
41 #define PLL_CON3_PLL_SHARED1 0x014c
[all …]
H A Dclk-exynos850.c36 /* Register Offset definitions for CMU_TOP (0x120e0000) */
37 #define PLL_LOCKTIME_PLL_MMC 0x0000
38 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
39 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
40 #define PLL_CON0_PLL_MMC 0x0100
41 #define PLL_CON3_PLL_MMC 0x010c
42 #define PLL_CON0_PLL_SHARED0 0x0140
43 #define PLL_CON3_PLL_SHARED0 0x014c
44 #define PLL_CON0_PLL_SHARED1 0x0180
45 #define PLL_CON3_PLL_SHARED1 0x018c
[all …]
/linux/arch/arm/mach-omap2/
H A Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
H A Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
H A Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
H A Dcm81xx.h13 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
14 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
15 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
16 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
19 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
20 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
21 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
24 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
25 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
26 #define TI81XX_CM_ETHERNET_CLKDM 0x0004
[all …]
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dcm1_7xx.h23 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
[all …]
H A Dprcm_mpu7xx.h24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
H A Dprcm_mpu54xx.h24 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
30 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
31 #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
32 #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
33 #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
34 #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
35 #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
38 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
39 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
52 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
H A Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/linux/sound/soc/mediatek/mt2701/
H A Dmt2701-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON3 0x000c
14 #define AUDIO_TOP_CON4 0x0010
15 #define AUDIO_TOP_CON5 0x0014
16 #define AFE_DAIBT_CON0 0x001c
17 #define AFE_MRGIF_CON 0x003c
18 #define AFE_HDMI_OUT_CON0 0x0370
19 #define AFE_HDMI_OUT_BASE 0x0374
20 #define AFE_HDMI_OUT_CUR 0x0378
21 #define AFE_HDMI_OUT_END 0x037
[all...]
/linux/drivers/net/phy/
H A Dmicrochip_t1s.c14 #define PHY_ID_LAN867X_REVB1 0x0007C162
15 #define PHY_ID_LAN867X_REVC1 0x0007C164
16 #define PHY_ID_LAN867X_REVC2 0x0007C165
17 #define PHY_ID_LAN867X_REVD0 0x0007C166
19 #define PHY_ID_LAN865X_REVB 0x0007C1B3
21 #define LAN867X_REG_STS2 0x0019
25 #define LAN865X_REG_CFGPARAM_ADDR 0x00D8
26 #define LAN865X_REG_CFGPARAM_DATA 0x00D9
27 #define LAN865X_REG_CFGPARAM_CTRL 0x00DA
28 #define LAN865X_REG_STS2 0x0019
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
14 0)
17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
[all …]
/linux/samples/bpf/
H A Dnet_shared.h9 #define ETH_P_802_3_MIN 0x0600
10 #define ETH_P_8021Q 0x8100
11 #define ETH_P_8021AD 0x88A8
12 #define ETH_P_IP 0x0800
13 #define ETH_P_IPV6 0x86DD
14 #define ETH_P_ARP 0x0806
17 #define TC_ACT_OK 0
/linux/arch/sparc/include/asm/
H A Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/linux/drivers/media/usb/dvb-usb-v2/
H A Drtl28xxu.h40 #define DEMOD 0x0000
41 #define USB 0x0100
42 #define SYS 0x0200
43 #define I2C 0x0300
44 #define I2C_DA 0x0600
46 #define CMD_WR_FLAG 0x0010
47 #define CMD_DEMOD_RD 0x0000
48 #define CMD_DEMOD_WR 0x0010
49 #define CMD_USB_RD 0x0100
50 #define CMD_USB_WR 0x0110
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa320.c26 MFP_ADDR_X(GPIO0, GPIO4, 0x0124),
27 MFP_ADDR_X(GPIO5, GPIO9, 0x028C),
28 MFP_ADDR(GPIO10, 0x0458),
29 MFP_ADDR_X(GPIO11, GPIO26, 0x02A0),
30 MFP_ADDR_X(GPIO27, GPIO48, 0x0400),
31 MFP_ADDR_X(GPIO49, GPIO62, 0x045C),
32 MFP_ADDR_X(GPIO63, GPIO73, 0x04B4),
33 MFP_ADDR_X(GPIO74, GPIO98, 0x04F0),
34 MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
35 MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674),
[all …]
H A Dpxa300.c26 MFP_ADDR_X(GPIO0, GPIO2, 0x00b4),
27 MFP_ADDR_X(GPIO3, GPIO26, 0x027c),
28 MFP_ADDR_X(GPIO27, GPIO98, 0x0400),
29 MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
30 MFP_ADDR_X(GPIO0_2, GPIO1_2, 0x0674),
31 MFP_ADDR_X(GPIO2_2, GPIO6_2, 0x02dc),
33 MFP_ADDR(nBE0, 0x0204),
34 MFP_ADDR(nBE1, 0x0208),
36 MFP_ADDR(nLUA, 0x0244),
37 MFP_ADDR(nLLA, 0x0254),
[all …]
/linux/include/uapi/linux/
H A Dapm_bios.h41 #define APM_STATE_READY 0x0000
42 #define APM_STATE_STANDBY 0x0001
43 #define APM_STATE_SUSPEND 0x0002
44 #define APM_STATE_OFF 0x0003
45 #define APM_STATE_BUSY 0x0004
46 #define APM_STATE_REJECT 0x0005
47 #define APM_STATE_OEM_SYS 0x0020
48 #define APM_STATE_OEM_DEV 0x0040
50 #define APM_STATE_DISABLE 0x0000
51 #define APM_STATE_ENABLE 0x0001
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
[all …]

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