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/linux/drivers/media/usb/gspca/
H A Dspca505.c23 #define IntelPCCameraPro 0
52 .priv = 0},
57 #define SPCA50X_REG_USB 0x02 /* spca505 501 */
59 #define SPCA50X_USB_CTRL 0x00 /* spca505 */
60 #define SPCA50X_CUSB_ENABLE 0x01 /* spca505 */
62 #define SPCA50X_REG_GLOBAL 0x03 /* spca505 */
63 #define SPCA50X_GMISC0_IDSEL 0x01 /* Global control device ID select spca505 */
64 #define SPCA50X_GLOBAL_MISC0 0x00 /* Global control miscellaneous 0 spca505 */
66 #define SPCA50X_GLOBAL_MISC1 0x01 /* 505 */
67 #define SPCA50X_GLOBAL_MISC3 0x03 /* 505 */
[all …]
H A Dnw80x.c159 * - 3rd byte: data length (=0 for end of sequence)
162 #define I2C0 0xff
165 0x04, 0x05, 0x01, 0x61,
166 0x04, 0x04, 0x01, 0x01,
167 0x04, 0x06, 0x01, 0x04,
168 0x04, 0x04, 0x03, 0x00, 0x00, 0x00,
169 0x05, 0x05, 0x01, 0x00,
170 0, 0, 0
173 0x04, 0x06, 0x01, 0xc0,
174 0x00, 0x00, 0x40, 0x10, 0x43, 0x00, 0xb4, 0x01, 0x10, 0x00, 0x4f,
[all …]
/linux/include/dt-bindings/input/
H A Dcros-ec-keyboard.h13 MATRIX_KEY(0x00, 0x02, KEY_F1) \
14 MATRIX_KEY(0x03, 0x02, KEY_F2) \
15 MATRIX_KEY(0x02, 0x02, KEY_F3) \
16 MATRIX_KEY(0x01, 0x02, KEY_F4) \
17 MATRIX_KEY(0x03, 0x04, KEY_F5) \
18 MATRIX_KEY(0x02, 0x04, KEY_F6) \
19 MATRIX_KEY(0x01, 0x04, KEY_F7) \
20 MATRIX_KEY(0x02, 0x09, KEY_F8) \
21 MATRIX_KEY(0x01, 0x09, KEY_F9) \
22 MATRIX_KEY(0x00, 0x04, KEY_F10)
[all …]
/linux/sound/soc/codecs/
H A Dwcd9335.h8 * In slimbus mode the reg base starts from 0x800.
9 * In i2s/i2c mode the reg base is 0x0.
12 #define WCD9335_REG_OFFSET(r) (r & 0xFF)
13 #define WCD9335_PAGE_OFFSET(r) ((r >> 8) & 0xFF)
15 /* Page-0 Registers */
16 #define WCD9335_PAGE0_PAGE_REGISTER WCD9335_REG(0x00, 0x000)
17 #define WCD9335_CODEC_RPM_CLK_GATE WCD9335_REG(0x00, 0x002)
18 #define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK GENMASK(1, 0)
19 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG WCD9335_REG(0x00, 0x003)
20 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0)
[all …]
/linux/include/linux/mfd/
H A Dpalmas.h24 #define PALMAS_CHIP_OLD_ID 0x0000
25 #define PALMAS_CHIP_ID 0xC035
26 #define PALMAS_CHIP_CHARGER_ID 0xC036
43 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
133 int ch3_current; /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */
135 /* Channel 0 current source can be used for battery detection.
139 int ch0_current; /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */
154 * 0: reload default values from OTP on warm reset
165 * 0: i2c selection of voltage
177 * 0: Off
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dwndwca7e.c25 NVVAL(NVCA7E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, 0) | in wndwca7e_image_clr()
28 PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0), in wndwca7e_image_clr()
31 return 0; in wndwca7e_image_clr()
37 const u32 iso0_hi = upper_32_bits(asyw->image.offset[0]); in wndwca7e_image_set()
38 const u32 iso0_lo = lower_32_bits(asyw->image.offset[0]); in wndwca7e_image_set()
51 PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_ISO(0), iso0_hi); in wndwca7e_image_set()
53 PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0), in wndwca7e_image_set()
77 SET_PLANAR_STORAGE(0), in wndwca7e_image_set()
78 NVVAL(NVCA7E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) | in wndwca7e_image_set()
79 NVVAL(NVCA7E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6)); in wndwca7e_image_set()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/linux/sound/pci/nm256/
H A Dnm256_coef.c2 #define NM_TOTAL_COEFF_COUNT 0x3158
5 0xFF, 0xFF, 0x2F, 0x00, 0x4B, 0xFF, 0xA5, 0x01, 0xEF, 0xFC, 0x21,
6 0x05, 0x87, 0xF7, 0x62, 0x11, 0xE9, 0x45, 0x5E, 0xF9, 0xB5, 0x01,
7 0xDE, 0xFF, 0xA4, 0xFF, 0x60, 0x00, 0xCA, 0xFF, 0x0D, 0x00, 0xFD,
8 0xFF, 0x36, 0x00, 0x36, 0xFF, 0xE6, 0x01, 0x3D, 0xFC, 0xD6, 0x06,
9 0x4C, 0xF3, 0xED, 0x20, 0x3D, 0x3D, 0x4A, 0xF3, 0x4E, 0x05, 0xB1,
10 0xFD, 0xE1, 0x00, 0xC3, 0xFF, 0x05, 0x00, 0x02, 0x00, 0xFD, 0xFF,
11 0x2A, 0x00, 0x5C, 0xFF, 0xAA, 0x01, 0x71, 0xFC, 0x07, 0x07, 0x7E,
12 0xF1, 0x44, 0x30, 0x44, 0x30, 0x7E, 0xF1, 0x07, 0x07, 0x71, 0xFC,
13 0xAA, 0x01, 0x5C, 0xFF, 0x2A, 0x00, 0xFD, 0xFF, 0x02, 0x00, 0x05,
[all …]
/linux/drivers/media/dvb-frontends/cxd2880/
H A Dcxd2880_dvbt2.h28 CXD2880_DVBT2_S1_BASE_SISO = 0x00,
29 CXD2880_DVBT2_S1_BASE_MISO = 0x01,
30 CXD2880_DVBT2_S1_NON_DVBT2 = 0x02,
31 CXD2880_DVBT2_S1_LITE_SISO = 0x03,
32 CXD2880_DVBT2_S1_LITE_MISO = 0x04,
33 CXD2880_DVBT2_S1_RSVD3 = 0x05,
34 CXD2880_DVBT2_S1_RSVD4 = 0x06,
35 CXD2880_DVBT2_S1_RSVD5 = 0x07,
36 CXD2880_DVBT2_S1_UNKNOWN = 0xff
40 CXD2880_DVBT2_BASE_S2_M2K_G_ANY = 0x00,
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-n950.dts27 pinctrl-0 = <&keypad_slide_pins>;
35 OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */
43 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
44 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
45 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
46 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
54 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - data0+ */
55 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - data0- */
56 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE1) /* dsi_dx1 - clk+ */
57 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE1) /* dsi_dy1 - clk- */
[all …]
/linux/fs/unicode/
H A Dutf8data.c_shipped8 0,
9 0x10100,
10 0x20000,
11 0x20100,
12 0x30000,
13 0x30100,
14 0x30200,
15 0x40000,
16 0x40100,
17 0x50000,
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2056.c24 #define B2056_INITTAB_ENTRY_OK 0x01
25 #define B2056_INITTAB_UPLOAD 0x02
39 [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
40 [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
41 [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
42 [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
43 [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
44 [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
45 [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
46 [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
[all …]
/linux/drivers/media/platform/st/sti/bdisp/
H A Dbdisp-hw.c37 bool src_420; /* is the src 4:2:0 chroma subsampled */
40 bool dst_420; /* is the dst 4:2:0 chroma subsampled */
52 .min = 0,
55 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
56 0x00, 0x00, 0xff, 0x07, 0x3d, 0xfc, 0x01, 0x00,
57 0x00, 0x01, 0xfd, 0x11, 0x36, 0xf9, 0x02, 0x00,
58 0x00, 0x01, 0xfb, 0x1b, 0x2e, 0xf9, 0x02, 0x00,
59 0x00, 0x01, 0xf9, 0x26, 0x26, 0xf9, 0x01, 0x00,
60 0x00, 0x02, 0xf9, 0x30, 0x19, 0xfb, 0x01, 0x00,
61 0x00, 0x02, 0xf9, 0x39, 0x0e, 0xfd, 0x01, 0x00,
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/linux/drivers/usb/misc/sisusbvga/
H A Dsisusb_tables.h58 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
59 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
60 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
61 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
62 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
63 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
64 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
65 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F
69 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
70 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
[all …]
/linux/kernel/bpf/preload/iterators/
H A Diterators.lskel-big-endian.h27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach()
29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach()
38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach()
40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach()
48 int ret = 0; in iterators_bpf__attach()
50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach()
51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach()
52 return ret < 0 ? ret : 0; in iterators_bpf__attach()
93 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
94 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
[all …]
/linux/drivers/hid/
H A Dhid-maltron.c26 0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */
27 0x09, 0x80, /* Usage (Sys Control) */
28 0xA1, 0x01, /* Collection (Application) */
29 0x85, 0x02, /* Report ID (2) */
30 0x75, 0x01, /* Report Size (1) */
31 0x95, 0x01, /* Report Count (1) */
32 0x15, 0x00, /* Logical Minimum (0) */
33 0x25, 0x01, /* Logical Maximum (1) */
34 0x09, 0x82, /* Usage (Sys Sleep) */
35 0x81, 0x06, /* Input (Data,Var,Rel) */
[all …]
/linux/arch/mips/pic32/pic32mzda/
H A Dearly_pin.h70 #define IN_RPD2 0x00
71 #define IN_RPG8 0x01
72 #define IN_RPF4 0x02
73 #define IN_RPD10 0x03
74 #define IN_RPF1 0x04
75 #define IN_RPB9 0x05
76 #define IN_RPB10 0x06
77 #define IN_RPC14 0x07
78 #define IN_RPB5 0x08
79 #define IN_RPC1 0x0A
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_n.c28 radio_type##_##jspace##0 : \
34 radio_type##_##jspace##0 : \
42 radio_type##_##jspace##0##_##reg_name : \
47 radio_type##_##jspace##0##_##reg_name : \
53 radio_type##_##reg_name##_##jspace##0 : \
58 radio_type##_##reg_name##_##jspace##0 : \
107 #define NPHY_RSSICAL_NB_TARGET 0
120 #define NPHY_RSSI_SXT(x) ((s8) (-((x) & 0x20) + ((x) & 0x1f)))
129 #define NPHY_N_GCTL 0x66
135 #define NPHY_PAPD_COMP_OFF 0
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-event_source-devices-dfl_fme13 event = "config:0-11" - event ID
19 fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff"
21 It shows this fab_mmio_read is a fabric type (0x02) event with
22 0x06 local event id for overall monitoring (portid=0xff).
43 Basic events (evtype=0x00)::
45 clock = "event=0x00,evtype=0x00,portid=0xff"
47 Cache events (evtype=0x01)::
49 cache_read_hit = "event=0x00,evtype=0x01,portid=0xff"
50 cache_read_miss = "event=0x01,evtype=0x01,portid=0xff"
51 cache_write_hit = "event=0x02,evtype=0x01,portid=0xff"
[all …]
/linux/include/linux/usb/
H A Daudio-v2.h8 * in http://www.usb.org/developers/devclass_docs/Audio2.0_final.zip
16 /* v1.0 and v2.0 of this standard have many things in common. For the rest
22 * From the USB Audio spec v2.0:
27 * present then the bit pair must be set to 0b00.
29 * set to 0b01. If a Control is also Host programmable, the bit
30 * pair must be set to 0b11. The value 0b10 is not allowed.
36 return (bmControls >> ((control - 1) * 2)) & 0x1; in uac_v2v3_control_is_readable()
41 return (bmControls >> ((control - 1) * 2)) & 0x2; in uac_v2v3_control_is_writeable()
49 __le16 bcdADC; /* 0x0200 */
79 #define UAC_CLOCK_SOURCE_TYPE_EXT 0x0
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-harmony.dts21 memory@0 {
22 reg = <0x00000000 0x40000000>;
49 pinctrl-0 = <&state_default>;
291 reg = <0x1a>;
298 micdet-cfg = <0>;
300 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
320 reg = <0x34>;
441 reg = <0x4c>;
449 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
451 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
[all …]
/linux/drivers/net/wireless/intersil/p54/
H A Dp54spi_eeprom.h19 0x47, 0x4d, 0x55, 0xaa, /* magic */
20 0x00, 0x00, /* pad */
21 0x00, 0x00, /* eeprom_pda_data_wrap length */
22 0x00, 0x00, 0x00, 0x00, /* arm opcode */
25 0x04, 0x00, 0x01, 0x01, /* PDR_MAC_ADDRESS */
26 0x00, 0x02, 0xee, 0xc0, 0xff, 0xee,
29 0x06, 0x00, 0x01, 0x10, /* PDR_INTERFACE_LIST */
30 0x00, 0x00, /* role */
31 0x0f, 0x00, /* if_id */
32 0x85, 0x00, /* variant = Longbow RF, 2GHz */
[all …]
/linux/drivers/video/fbdev/sis/
H A D300vtbl.h55 {0x6a,0x2212,0x0102,SIS_RI_800x600, 0x00,0x00,0x00,0x00,0x00,-1}, /* 800x600x? */
56 {0x2e,0x0a1b,0x0101,SIS_RI_640x480, 0x00,0x00,0x00,0x00,0x08,-1},
57 {0x2f,0x021b,0x0100,SIS_RI_640x400, 0x00,0x00,0x00,0x00,0x10,-1}, /* 640x400x8 */
58 {0x30,0x2a1b,0x0103,SIS_RI_800x600, 0x00,0x00,0x00,0x00,0x00,-1},
59 {0x31,0x4a1b,0x0000,SIS_RI_720x480, 0x00,0x00,0x00,0x00,0x11,-1}, /* 720x480x8 */
60 {0x32,0x6a1b,0x0000,SIS_RI_720x576, 0x00,0x00,0x00,0x00,0x12,-1}, /* 720x576x8 */
61 {0x33,0x4a1d,0x0000,SIS_RI_720x480, 0x00,0x00,0x00,0x00,0x11,-1}, /* 720x480x16 */
62 {0x34,0x6a1d,0x0000,SIS_RI_720x576, 0x00,0x00,0x00,0x00,0x12,-1}, /* 720x576x16 */
63 {0x35,0x4a1f,0x0000,SIS_RI_720x480, 0x00,0x00,0x00,0x00,0x11,-1}, /* 720x480x32 */
64 {0x36,0x6a1f,0x0000,SIS_RI_720x576, 0x00,0x00,0x00,0x00,0x12,-1}, /* 720x576x32 */
[all …]
/linux/drivers/misc/cardreader/
H A Drts5261.h14 #define rts5261_vendor_setting_valid(reg) ((reg) & 0x010000)
16 (((~(reg) >> 28) & 0x02) | (((reg) >> 28) & 0x01))
17 #define rts5261_reg_check_reverse_socket(reg) ((reg) & 0x04)
18 #define rts5261_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) & 0x03)
19 #define rts5261_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) & 0x03)
20 #define rts5261_reg_to_rtd3(reg) ((reg) & 0x08)
21 #define rts5261_reg_check_mmc_support(reg) ((reg) & 0x10)
23 #define RTS5261_AUTOLOAD_CFG0 0xFF7B
24 #define RTS5261_AUTOLOAD_CFG1 0xFF7C
25 #define RTS5261_AUTOLOAD_CFG2 0xFF7D
[all …]

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