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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,qcm2290-dpu.yaml61 reg = <0x05e01000 0x8f000>,
62 <0x05eb0000 0x2008>;
76 interrupts = <0>;
80 #size-cells = <0>;
82 port@0 {
83 reg = <0>;
H A Dqcom,sm6115-dpu.yaml63 reg = <0x05e01000 0x8f000>,
64 <0x05eb0000 0x2008>;
79 interrupts = <0>;
83 #size-cells = <0>;
85 port@0 {
86 reg = <0>;
H A Dqcom,qcm2290-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
93 reg = <0x05e00000 0x1000>;
110 iommus = <&apps_smmu 0x420 0x2>,
111 <&apps_smmu 0x421 0x0>;
116 reg = <0x05e0100
[all...]
H A Dqcom,sm6115-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
90 reg = <0x05e00000 0x1000>;
101 iommus = <&apps_smmu 0x420 0x2>,
102 <&apps_smmu 0x421 0x0>;
107 reg = <0x05e0100
[all...]
H A Dqcom,sm6375-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
86 reg = <0x05e00000 0x1000>;
100 iommus = <&apps_smmu 0x820 0x2>;
107 reg = <0x05e01000 0x8e030>,
108 <0x05eb0000 0x2008>;
133 interrupts = <0>;
137 #size-cells = <0>;
139 port@0 {
[all …]
H A Ddpu-qcm2290.yaml74 "^display-controller@[0-9a-f]+$":
129 port@0:
134 - port@0
171 reg = <0x05e00000 0x1000>;
186 iommus = <&apps_smmu 0x420 0x2>,
187 <&apps_smmu 0x421 0x0>;
192 reg = <0x05e01000 0x8f000>,
193 <0x05eb0000 0x2008>;
207 interrupts = <0>;
211 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm6125.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
[all …]
H A Dqcm2290.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
49 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
67 reg = <0x0 0x1>;
68 clocks = <&cpufreq_hw 0>;
73 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6115.dtsi30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
47 clocks = <&cpufreq_hw 0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x1>;
66 clocks = <&cpufreq_hw 0>;
71 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]