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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,qcm2290-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
93 reg = <0x05e00000 0x1000>;
110 iommus = <&apps_smmu 0x420 0x2>,
111 <&apps_smmu 0x421 0x0>;
116 reg = <0x05e01000 0x8f000>,
117 <0x05eb0000 0x2008>;
131 interrupts = <0>;
135 #size-cells = <0>;
[all …]
H A Dqcom,sm6115-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
90 reg = <0x05e00000 0x1000>;
101 iommus = <&apps_smmu 0x420 0x2>,
102 <&apps_smmu 0x421 0x0>;
107 reg = <0x05e01000 0x8f000>,
108 <0x05eb0000 0x2008>;
123 interrupts = <0>;
127 #size-cells = <0>;
[all …]
H A Dqcom,sm6125-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
86 reg = <0x05e00000 0x1000>;
102 iommus = <&apps_smmu 0x400 0x0>;
110 reg = <0x05e01000 0x83208>,
111 <0x05eb0000 0x2008>;
115 interrupts = <0>;
139 #size-cells = <0>;
141 port@0 {
[all …]
H A Dqcom,sm6375-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
86 reg = <0x05e00000 0x1000>;
100 iommus = <&apps_smmu 0x820 0x2>;
107 reg = <0x05e01000 0x8e030>,
108 <0x05eb0000 0x2008>;
133 interrupts = <0>;
137 #size-cells = <0>;
139 port@0 {
[all …]
/linux/drivers/video/fbdev/
H A Dsunxvr500.c58 ep->width = of_getintprop_default(ep->of_node, "width", 0); in e3d_get_props()
59 ep->height = of_getintprop_default(ep->of_node, "height", 0); in e3d_get_props()
68 return 0; in e3d_get_props()
72 * 0x04000000, the following video layout register values:
74 * RAMDAC_VID_WH 0x03ff04ff
75 * RAMDAC_VID_CFG 0x1a0b0088
76 * RAMDAC_VID_32FB_0 0x04000000
77 * RAMDAC_VID_32FB_1 0x04800000
78 * RAMDAC_VID_8FB_0 0x05000000
79 * RAMDAC_VID_8FB_1 0x05200000
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-hikey.dts32 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
33 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
34 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
35 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
36 * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
37 * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
39 memory@0 {
41 reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
42 <0x00000000 0x05f00000 0x00000000 0x00001000>,
43 <0x00000000 0x05f02000 0x00000000 0x00efd000>,
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
[all …]
H A Dqcm2290.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
49 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
67 reg = <0x0 0x1>;
68 clocks = <&cpufreq_hw 0>;
73 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6115.dtsi30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
47 clocks = <&cpufreq_hw 0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x1>;
66 clocks = <&cpufreq_hw 0>;
71 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]