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/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
91 - description: common_s0 DSS Shared common 0
113 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
165 <0x04a50000 0x10000>, /* vid1 */
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am64-mcu.dtsi16 reg = <0x00 0x4800000 0x00 0x400>;
26 reg = <0x00 0x4810000 0x00 0x400>;
36 reg = <0x00 0x4820000 0x00 0x400>;
46 reg = <0x00 0x4830000 0x00 0x400>;
56 reg = <0x00 0x04a00000 0x00 0x100>;
59 clocks = <&k3_clks 149 0>;
66 reg = <0x00 0x04a10000 0x00 0x100>;
69 clocks = <&k3_clks 160 0>;
76 reg = <0x00 0x04900000 0x00 0x100>;
79 #size-cells = <0>;
[all …]
H A Dk3-am62-mcu.dtsi12 reg = <0x00 0x04084000 0x00 0x88>;
15 pinctrl-single,function-mask = <0xffffffff>;
21 reg = <0x00 0x4100000 0x00 0x1000>;
23 ti,esm-pins = <0>, <1>, <2>, <85>;
33 reg = <0x00 0x4800000 0x00 0x400>;
43 reg = <0x00 0x4810000 0x00 0x400>;
53 reg = <0x00 0x4820000 0x00 0x400>;
63 reg = <0x00 0x4830000 0x00 0x400>;
73 reg = <0x00 0x04a00000 0x00 0x100>;
76 clocks = <&k3_clks 149 0>;
[all …]
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Daldebaran_ip_offset.h35 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } },
36 { { 0, 0, 0, 0, 0, 0 } },
37 { { 0, 0, 0, 0, 0, 0 } },
38 { { 0, 0, 0, 0, 0, 0 } },
39 { { 0, 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0, 0 } } } };
42 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
43 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
44 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125.dtsi25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
58 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
76 reg = <0x0 0x3>;
85 reg = <0x0 0x100>;
99 reg = <0x0 0x101>;
[all …]
H A Dsm6115.dtsi34 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
69 reg = <0x0 0x1>;
70 clocks = <&cpufreq_hw 0>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]