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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,qcm2290.yaml64 reg = <0x01880000 0x60200>;
85 reg = <0x01900000 0x8200>;
91 reg = <0x04480000 0x80000>;
/linux/drivers/net/wireless/ath/ath5k/
H A Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Dyellow_carp_offset.h19 static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
20 { { 0, 0, 0, 0, 0, 0 } },
21 { { 0, 0, 0, 0, 0, 0 } },
22 { { 0, 0, 0, 0, 0, 0 } },
23 { { 0, 0, 0, 0, 0, 0 } },
24 { { 0, 0, 0, 0, 0, 0 } },
25 { { 0, 0, 0, 0, 0, 0 } } } };
26 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
27 { { 0, 0, 0, 0, 0, 0 } },
28 { { 0, 0, 0, 0, 0, 0 } },
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7722.c30 .addr = 0xffe0000c,
32 .mid_rid = 0x21,
35 .addr = 0xffe00014,
37 .mid_rid = 0x22,
40 .addr = 0xffe1000c,
42 .mid_rid = 0x25,
45 .addr = 0xffe10014,
47 .mid_rid = 0x26,
50 .addr = 0xffe2000c,
52 .mid_rid = 0x29,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dqcm2290.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x0>;
49 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
67 reg = <0x0 0x1>;
68 clocks = <&cpufreq_hw 0>;
73 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6115.dtsi30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0 0x0>;
47 clocks = <&cpufreq_hw 0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x1>;
66 clocks = <&cpufreq_hw 0>;
71 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]