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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dqcom,msm8916-mss-pil.yaml307 reg = <0x04080000 0x100>, <0x04020000 0x40>;
311 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
317 qcom,smem-states = <&hexagon_smp2p_out 0>;
319 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
331 resets = <&scm 0>;
339 qcom,smd-edge = <0>;
/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dcv18xx.dtsi17 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
47 #clock-cells = <0>;
59 reg = <0x03002000 0x1000>;
66 reg = <0x3020000 0x1000>;
68 #size-cells = <0>;
70 porta: gpio-controller@0 {
75 reg = <0>;
84 reg = <0x3021000 0x1000>;
[all …]
H A Dcv180x.dtsi19 #clock-cells = <0>;
30 reg = <0x3003000 0x1000>;
36 reg = <0x3009800 0x4>;
38 #size-cells = <0>;
40 mux-mask = <0x80>;
43 internal_mdio: mdio@0 {
45 #size-cells = <0>;
46 reg = <0>;
48 internal_ephy: phy@0 {
56 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a100.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
72 #clock-cells = <0>;
80 #clock-cells = <0>;
87 #clock-cells = <0>;
106 ranges = <0 0 0 0x3fffffff>;
[all …]
H A Dsun55i-a523.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x000>;
32 reg = <0x100>;
39 reg = <0x200>;
46 reg = <0x300>;
53 reg = <0x400>;
60 reg = <0x500>;
67 reg = <0x600>;
74 reg = <0x700>;
[all …]
H A Dsun50i-h616.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
30 i-cache-size = <0x8000>;
33 d-cache-size = <0x8000>;
46 i-cache-size = <0x8000>;
49 d-cache-size = <0x8000>;
62 i-cache-size = <0x8000>;
65 d-cache-size = <0x8000>;
78 i-cache-size = <0x8000>;
[all …]
H A Dsun50i-h6.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
27 reg = <0>;
31 i-cache-size = <0x8000>;
34 d-cache-size = <0x8000>;
47 i-cache-size = <0x8000>;
50 d-cache-size = <0x8000>;
63 i-cache-size = <0x8000>;
66 d-cache-size = <0x8000>;
79 i-cache-size = <0x8000>;
[all …]
/freebsd/sys/dev/mfi/
H A Dmfireg.h72 #define MFI_IMSG0 0x10 /* Inbound message 0 */
73 #define MFI_IMSG1 0x14 /* Inbound message 1 */
74 #define MFI_OMSG0 0x18 /* Outbound message 0 */
75 #define MFI_OMSG1 0x1c /* Outbound message 1 */
76 #define MFI_IDB 0x20 /* Inbound doorbell */
77 #define MFI_ISTS 0x24 /* Inbound interrupt status */
78 #define MFI_IMSK 0x28 /* Inbound interrupt mask */
79 #define MFI_ODB 0x2c /* Outbound doorbell */
80 #define MFI_OSTS 0x30 /* Outbound interrupt status */
81 #define MFI_OMSK 0x34 /* Outbound interrupt mask */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8953.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
42 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0x0>;
59 reg = <0x1>;
71 reg = <0x2>;
83 reg = <0x3>;
95 reg = <0x100>;
107 reg = <0x101>;
[all …]
H A Dmsm8939.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
50 cpu-release-addr = /bits/ 64 <0>;
51 reg = <0x100>;
69 cpu-release-addr = /bits/ 64 <0>;
70 reg = <0x101>;
83 cpu-release-addr = /bits/ 64 <0>;
84 reg = <0x102>;
97 cpu-release-addr = /bits/ 64 <0>;
[all …]
H A Dmsm8916.dtsi28 reg = <0 0x80000000 0 0>;
37 reg = <0x0 0x86000000 0x0 0x300000>;
43 reg = <0x0 0x86300000 0x0 0x100000>;
51 reg = <0x0 0x86400000 0x0 0x100000>;
56 reg = <0x0 0x86500000 0x0 0x180000>;
61 reg = <0x0 0x86680000 0x0 0x80000>;
67 reg = <0x0 0x86700000 0x0 0xe0000>;
74 reg = <0x0 0x867e0000 0x0 0x20000>;
86 * alignment = <0x0 0x400000>;
87 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]