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/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,wcd939x-sdw.yaml49 #size-cells = <0>;
50 reg = <0x03210000 0x2000>;
51 wcd938x_rx: codec@0,4 {
53 reg = <0 4>;
60 #size-cells = <0>;
61 reg = <0x03230000 0x2000>;
62 wcd938x_tx: codec@0,3 {
64 reg = <0 3>;
H A Dqcom,wcd938x-sdw.yaml50 #size-cells = <0>;
51 reg = <0x03210000 0x2000>;
52 wcd938x_rx: codec@0,4 {
54 reg = <0 4>;
61 #size-cells = <0>;
62 reg = <0x03230000 0x2000>;
63 wcd938x_tx: codec@0,3 {
65 reg = <0 3>;
H A Dqcom,wcd938x.yaml64 #size-cells = <0>;
65 reg = <0x03210000 0x2000>;
66 wcd938x_rx: codec@0,4 {
68 reg = <0 4>;
75 #size-cells = <0>;
76 reg = <0x03230000 0x2000>;
77 wcd938x_tx: codec@0,3 {
79 reg = <0 3>;
H A Dqcom,wcd937x.yaml43 pinctrl-0 = <&wcd_reset_n>;
62 reg = <0x03210000 0x2000>;
64 #size-cells = <0>;
65 wcd937x_rx: codec@0,4 {
67 reg = <0 4>;
73 reg = <0x03230000 0x2000>;
75 #size-cells = <0>;
76 wcd937x_tx: codec@0,3 {
78 reg = <0 3>;
H A Dqcom,wcd939x.yaml76 #size-cells = <0>;
77 reg = <0x03210000 0x2000>;
78 wcd939x_rx: codec@0,4 {
80 reg = <0 4>;
87 #size-cells = <0>;
88 reg = <0x03230000 0x2000>;
89 wcd938x_tx: codec@0,3 {
91 reg = <0 3>;
/linux/Documentation/devicetree/bindings/soundwire/
H A Dqcom,soundwire.yaml69 const: 0
85 Value of 0xff indicates that this option is not implemented
96 Value of 0xff indicates that this option is not implemented
107 Value of 0xffff indicates that this option is not implemented
118 Value of 0xff indicates that this option is not implemented
129 Value of 0xff indicates that this option is not implemented
140 Value of 0xff indicates that this option is not implemented
150 0 to indicate Blocks are per Channel
153 Value of 0xff indicates that this option is not implemented
160 - minimum: 0
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8450.dtsi40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 cpu0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]
H A Dsc7280.dtsi83 #clock-cells = <0>;
89 #clock-cells = <0>;
100 reg = <0x0 0x004cd000 0x0 0x1000>;
104 reg = <0x0 0x80000000 0x0 0x600000>;
109 reg = <0x0 0x80600000 0x0 0x200000>;
114 reg = <0x0 0x80800000 0x0 0x60000>;
119 reg = <0x0 0x80860000 0x0 0x20000>;
125 reg = <0x0 0x80884000 0x0 0x10000>;
130 reg = <0x0 0x808ff000 0x0 0x1000>;
135 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi31 bus@0 {
36 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
40 reg = <0x0 0x00100000 0x0 0xf000>,
41 <0x0 0x0010f000 0x0 0x1000>;
47 reg = <0x0 0x02080000 0x0 0x00121000>;
48 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
70 reg = <0x0 0x02200000 0x0 0x10000>,
71 <0x0 0x02210000 0x0 0x10000>;
124 gpio-ranges = <&pinmux 0 0 164>;
129 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]