/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
H A D | nvidia,tegra186-mc.yaml | 27 pattern: "^memory-controller@[0-9a-f]+$" 62 "^external-memory-controller@[0-9a-f]+$": 95 const: 0 244 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 245 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 246 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 247 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 248 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 249 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 256 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; [all …]
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/freebsd/contrib/llvm-project/compiler-rt/lib/xray/ |
H A D | xray_loongarch64.cpp | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 65 // jirl ra, t0, 0 ; call the tracing hook in patchSled() 79 uint32_t LoTracingHookAddr = reinterpret_cast<int64_t>(TracingHook) & 0xfff; in patchSled() 81 (reinterpret_cast<int64_t>(TracingHook) >> 12) & 0xfffff; in patchSled() 83 (reinterpret_cast<int64_t>(TracingHook) >> 32) & 0xfffff; in patchSled() 85 (reinterpret_cast<int64_t>(TracingHook) >> 52) & 0xfff; in patchSled() 86 uint32_t LoFunctionID = FuncId & 0xfff; in patchSled() 87 uint32_t HiFunctionID = (FuncId >> 12) & 0xfffff; in patchSled() 88 Address[1] = encodeInstruction2RIx(0x29c00000, RegNum::RN_RA, RegNum::RN_SP, in patchSled() 89 0x8); // st.d ra, sp, 8 in patchSled() [all …]
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/freebsd/stand/powerpc/ofw/ |
H A D | ppc-common.ldscript | 4 PROVIDE (__stack = 0); 12 . = 0x02c00000 + SIZEOF_HEADERS; 45 } =0 48 .init : { *(.init) } =0 49 .fini : { *(.fini) } =0 55 . = ((. + 0x1000) & ~(0x1000 - 1)); 110 .stab 0 : { *(.stab) } 111 .stabstr 0 : { *(.stabstr) } 114 of the section so we begin them at 0. */ 116 .debug 0 : { *(.debug) } [all …]
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/freebsd/sys/dev/qlnx/qlnxe/ |
H A D | ecore_init_values.h | 35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */ 36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */ 37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */ 38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */ 40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */ 41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */ 42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */ 43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */ 44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */ 45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */ [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/ |
H A D | tegra186.dtsi | 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 27 reg = <0x0 0x220000 [all...] |
H A D | tegra194.dtsi | 20 bus@0 { 25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 29 reg = <0x0 0x00100000 0x [all...] |
H A D | tegra234.dtsi | 19 bus@0 { 24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 28 reg = <0x0 0x00100000 0x0 0xf000>, 29 <0x0 0x0010f000 0x0 0x1000>; 35 reg = <0x0 0x02080000 0x0 0x00121000>; 36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 58 reg = <0x0 0x02200000 0x0 0x10000>, 59 <0x0 0x02210000 0x0 0x10000>; 112 gpio-ranges = <&pinmux 0 0 164>; 117 reg = <0x0 0x2430000 0x0 0x19100>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/ |
H A D | stingray.dtsi | 43 #size-cells = <0>; 45 cpu@0 { 48 reg = <0x0 0x0>; 56 reg = <0x0 0x1>; 64 reg = <0x0 0x100>; 72 reg = <0x0 0x101>; 80 reg = <0x0 0x200>; 88 reg = <0x0 0x201>; 96 reg = <0x0 0x300>; 104 reg = <0x0 0x301>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | ipq8074.dtsi | 21 #clock-cells = <0>; 27 #clock-cells = <0>; 33 #size-cells = <0>; 35 CPU0: cpu@0 { 38 reg = <0x0>; 47 reg = <0x1>; 55 reg = <0x2>; 63 reg = <0x3>; 90 reg = <0x0 0x4a600000 0x0 0x400000>; 95 reg = <0x0 0x4aa00000 0x0 0x100000>; [all …]
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H A D | qcs404.dtsi | 24 #clock-cells = <0>; 30 #clock-cells = <0>; 37 #size-cells = <0>; 42 reg = <0x100>; 56 reg = <0x101>; 70 reg = <0x102>; 84 reg = <0x103>; 104 CPU_SLEEP_0: cpu-sleep-0 { 107 arm,psci-suspend-param = <0x40000003>; 161 reg = <0 0x80000000 0 0>; [all …]
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H A D | msm8976.dtsi | 26 #clock-cells = <0>; 32 #size-cells = <0>; 34 CPU0: cpu@0 { 37 reg = <0x0>; 48 reg = <0x1>; 59 reg = <0x2>; 70 reg = <0x3>; 81 reg = <0x100>; 92 reg = <0x101>; 103 reg = <0x102>; [all …]
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H A D | msm8953.dtsi | 25 #clock-cells = <0>; 31 #clock-cells = <0>; 39 #size-cells = <0>; 41 CPU0: cpu@0 { 44 reg = <0x0>; 54 reg = <0x1>; 64 reg = <0x2>; 74 reg = <0x3>; 84 reg = <0x100>; 94 reg = <0x101>; [all …]
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H A D | msm8939.dtsi | 30 #clock-cells = <0>; 36 #clock-cells = <0>; 43 #size-cells = <0>; 49 reg = <0x100>; 67 reg = <0x101>; 80 reg = <0x102>; 93 reg = <0x103>; 102 CPU4: cpu@0 { 106 reg = <0x0>; 124 reg = <0x1>; [all …]
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H A D | msm8916.dtsi | 27 reg = <0 0x80000000 0 0>; 36 reg = <0x0 0x86000000 0x0 0x300000>; 42 reg = <0x0 0x86300000 0x0 0x100000>; 50 reg = <0x0 0x86400000 0x0 0x100000>; 55 reg = <0x0 0x86500000 0x0 0x180000>; 60 reg = <0x0 0x86680000 0x0 0x80000>; 66 reg = <0x0 0x86700000 0x0 0xe0000>; 73 reg = <0x0 0x867e0000 0x0 0x20000>; 85 * alignment = <0x0 0x400000>; 86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; [all …]
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H A D | sc8180x.dtsi | 29 #clock-cells = <0>; 35 #clock-cells = <0>; 43 #size-cells = <0>; 45 CPU0: cpu@0 { 48 reg = <0x0 0x0>; 52 qcom,freq-domain = <&cpufreq_hw 0>; 59 clocks = <&cpufreq_hw 0>; 77 reg = <0x0 0x100>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 88 clocks = <&cpufreq_hw 0>; [all …]
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H A D | sm8150.dtsi | 34 #clock-cells = <0>; 41 #clock-cells = <0>; 49 #size-cells = <0>; 51 CPU0: cpu@0 { 54 reg = <0x0 0x0>; 55 clocks = <&cpufreq_hw 0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 83 reg = <0x0 0x100>; 84 clocks = <&cpufreq_hw 0>; [all …]
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/freebsd/contrib/llvm-project/lld/ELF/Arch/ |
H A D | LoongArch.cpp | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 48 SUB_W = 0x00110000, 49 SUB_D = 0x00118000, 50 BREAK = 0x002a0000, 51 SRLI_W = 0x00448000, 52 SRLI_D = 0x00450000, 53 ADDI_W = 0x02800000, 54 ADDI_D = 0x02c00000, 55 ANDI = 0x03400000, 56 PCADDU12I = 0x1c000000, [all …]
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/freebsd/contrib/llvm-project/libcxx/include/__format/ |
H A D | escaped_output_table.h | 4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 108 /// - bits [0, 13] The size of the range, allowing 16384 elements. 113 0x00000020 /* 00000000 - 00000020 [ 33] */, 114 0x001fc021 /* 0000007f - 000000a0 [ 34] */, 115 0x002b4000 /* 000000ad - 000000ad [ 1] */, 116 0x00de0001 /* 00000378 - 00000379 [ 2] */, 117 0x00e00003 /* 00000380 - 00000383 [ 4] */, 118 0x00e2c000 /* 0000038b - 0000038b [ 1] */, 119 0x00e34000 /* 0000038d - 0000038d [ 1] */, 120 0x00e88000 /* 000003a2 - 000003a2 [ 1] */, [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchInstrInfo.td | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 18 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, 20 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 24 def SDT_LoongArchCall : SDTypeProfile<0, -1, [SDTCisVT<0, GRLenVT>]>; 26 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64> 30 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>, 35 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3> 39 def SDT_LoongArchVI : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>; 41 def SDT_LoongArchCsrrd : SDTypeProfile<1, 1, [SDTCisInt<0>, 43 def SDT_LoongArchCsrwr : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, [all …]
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
H A D | EmulateInstructionARM.cpp | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 39 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC) in LLDB_PLUGIN_DEFINE_ADV() 47 ::memset(®_info, 0, sizeof(RegisterInfo)); in LLDB_PLUGIN_DEFINE_ADV() 234 // FPA Registers 0-7 in LLDB_PLUGIN_DEFINE_ADV() 260 // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator in LLDB_PLUGIN_DEFINE_ADV() 261 // register 0 - 7 (they do overlap with wCGR0 - wCGR7) in LLDB_PLUGIN_DEFINE_ADV() 287 // Intel wireless MMX data registers 0 - 15 in LLDB_PLUGIN_DEFINE_ADV() 423 // Intel wireless MMX control register in co-processor 0 - 7 in LLDB_PLUGIN_DEFINE_ADV() 604 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition. 609 return 0; in CountITSize() [all …]
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/freebsd/sys/dev/ispfw/ |
H A D | asm_2400.h | 33 0x0401f1be, 0x00112000, 0x00100000, 0x0000c79b, 34 0x00000008, 0x00000007, 0x00000000, 0x00009496, 35 0x00000003, 0x00000000, 0x20434f50, 0x59524947, 36 0x48542032, 0x30313720, 0x514c4f47, 0x49432043, 37 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350, 38 0x32347878, 0x20466972, 0x6d776172, 0x65202020, 39 0x56657273, 0x696f6e20, 0x2020382e, 0x30372e30, 40 0x30202024, 0x00000000, 0x00000000, 0x00000000, 41 0x00000000, 0x00000000, 0x00000000, 0x00000000, 42 0x00000000, 0x00000000, 0x00000000, 0x00000000, [all …]
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/freebsd/tools/test/iconv/ref/ |
H A D | UTF-32BE-rev | 1 0x00 = 0x00000000 2 0x01 = 0x01000000 3 0x02 = 0x02000000 4 0x03 = 0x03000000 5 0x04 = 0x04000000 6 0x05 = 0x05000000 7 0x06 = 0x06000000 8 0x07 = 0x07000000 9 0x08 = 0x08000000 10 0x09 = 0x09000000 [all …]
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