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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra210-pinmux.yaml122 reg = <0x700008d4 0x02a8>, /* Pad control registers */
123 <0x70003000 0x1000>; /* Mux registers */
126 pinctrl-0 = <&state_boot>;
/freebsd/contrib/tcpdump/
H A Dchecksum.c40 if accum & 0x400:
41 accum ^= 0x633
46 sys.stdout.write("0x%04x, " % crc_table[i*8+j])
52 0x0000, 0x0233, 0x0255, 0x0066, 0x0299, 0x00aa, 0x00cc, 0x02ff,
53 0x0301, 0x0132, 0x0154, 0x0367, 0x0198, 0x03ab, 0x03cd, 0x01fe,
54 0x0031, 0x0202, 0x0264, 0x0057, 0x02a8, 0x009b, 0x00fd, 0x02ce,
55 0x0330, 0x0103, 0x0165, 0x0356, 0x01a9, 0x039a, 0x03fc, 0x01cf,
56 0x0062, 0x0251, 0x0237, 0x0004, 0x02fb, 0x00c8, 0x00ae, 0x029d,
57 0x0363, 0x0150, 0x0136, 0x0305, 0x01fa, 0x03c9, 0x03af, 0x019c,
58 0x0053, 0x0260, 0x0206, 0x0035, 0x02ca, 0x00f9, 0x009f, 0x02ac,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am642-phyboard-electra-rdk.dts45 pinctrl-0 = <&can_tc1_pins_default>;
46 #phy-cells = <0>;
54 pinctrl-0 = <&can_tc2_pins_default>;
55 #phy-cells = <0>;
64 pinctrl-0 = <&icssg0_rgmii1_pins_default>, <&icssg0_rgmii2_pins_default>;
67 interrupts = <24 0 2>, <25 1 3>;
78 dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
79 <&main_pktdma 0xc101 15>, /* egress slice 0 */
80 <&main_pktdma 0xc102 15>, /* egress slice 0 */
81 <&main_pktdma 0xc103 15>, /* egress slice 0 */
[all …]
H A Dk3-am642-sr-som.dtsi31 pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>;
51 * interrupts 8/9 via channels 0/1 to host interrupts 0/1.
57 interrupts = <24 0 2>, <25 1 3>;
60 dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
61 <&main_pktdma 0xc201 15>, /* egress slice 0 */
62 <&main_pktdma 0xc202 15>, /* egress slice 0 */
63 <&main_pktdma 0xc203 15>, /* egress slice 0 */
64 <&main_pktdma 0xc204 15>, /* egress slice 1 */
65 <&main_pktdma 0xc205 15>, /* egress slice 1 */
66 <&main_pktdma 0xc206 15>, /* egress slice 1 */
[all …]
H A Dk3-am642-sk.dts40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
49 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
50 alignment = <0x1000>;
56 reg = <0x00 0xa0000000 0x00 0x100000>;
62 reg = <0x00 0xa0100000 0x00 0xf00000>;
68 reg = <0x00 0xa1000000 0x00 0x100000>;
74 reg = <0x00 0xa1100000 0x00 0xf00000>;
80 reg = <0x00 0xa2000000 0x00 0x100000>;
86 reg = <0x00 0xa2100000 0x00 0xf00000>;
92 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am642-evm.dts42 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
51 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
52 alignment = <0x1000>;
58 reg = <0x00 0xa0000000 0x00 0x100000>;
64 reg = <0x00 0xa0100000 0x00 0xf00000>;
70 reg = <0x00 0xa1000000 0x00 0x100000>;
76 reg = <0x00 0xa1100000 0x00 0xf00000>;
82 reg = <0x00 0xa2000000 0x00 0x100000>;
88 reg = <0x00 0xa2100000 0x00 0xf00000>;
94 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am642-tqma64xxl-mbax4xxl.dts50 pinctrl-0 = <&mcu_gpio_keys_pins>;
62 pinctrl-0 = <&mcu_gpio_leds_pins>;
64 led-0 {
79 pinctrl-0 = <&pru_icssg1_rgmii1_pins>, <&pru_icssg1_rgmii2_pins>;
81 interrupts = <24 0 2>, <25 1 3>;
83 dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
84 <&main_pktdma 0xc201 15>, /* egress slice 0 */
85 <&main_pktdma 0xc202 15>, /* egress slice 0 */
86 <&main_pktdma 0xc203 15>, /* egress slice 0 */
87 <&main_pktdma 0xc204 15>, /* egress slice 1 */
[all …]
/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
40 clock-frequency = <0>;
44 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
54 clock-frequency = <0>;
[all …]
/freebsd/share/i18n/csmapper/CNS/
H A DUCS@SIP%CNS11643-6.src5 SRC_ZONE 0x0003 - 0xFA17
7 DST_INVALID 0xFFFF
13 # Unicode version: 5.0.0
47 0x0003 = 0x212F
48 0x0004 = 0x212D
49 0x0005 = 0x212E
50 0x0007 = 0x2142
51 0x0008 = 0x2143
52 0x0012 = 0x222B
53 0x0018 = 0x2340
[all …]
H A DCNS11643-6%UCS@SIP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_ILSEQ 0xFFFE
13 # Unicode version: 5.0.0
47 0x2121 = 0xF802
48 0x2122 = 0x0062
49 0x2124 = 0x0088
50 0x2125 = 0x00D0
51 0x2126 = 0x00CF
52 0x2127 = 0x011E
53 0x2128 = 0x011F
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-16BE-rev1 0x00 = 0x0000
2 0x01 = 0x0100
3 0x02 = 0x0200
4 0x03 = 0x0300
5 0x04 = 0x0400
6 0x05 = 0x0500
7 0x06 = 0x0600
8 0x07 = 0x0700
9 0x08 = 0x0800
10 0x09 = 0x0900
[all …]
H A DUTF-16LE-rev1 0x00 = 0x0000
2 0x01 = 0x0001
3 0x02 = 0x0002
4 0x03 = 0x0003
5 0x04 = 0x0004
6 0x05 = 0x0005
7 0x06 = 0x0006
8 0x07 = 0x0007
9 0x08 = 0x0008
10 0x09 = 0x0009
[all …]
H A DBIG5HKSCS-rev1 0x00 = 0x00
2 0x01 = 0x01
3 0x02 = 0x02
4 0x03 = 0x03
5 0x04 = 0x04
6 0x05 = 0x05
7 0x06 = 0x06
8 0x07 = 0x07
9 0x08 = 0x08
10 0x09 = 0x09
[all …]
/freebsd/share/i18n/csmapper/GB/
H A DGB18030%UCS@BMP.src30 SRC_ZONE 0x81-0x84 / 0x30-0x39 / 0x81-0xFE / 0x30-0x39 / 8
32 DST_ILSEQ 0xFFFE
71 # for (i = 0; i < ncharset; ++i) {
74 # charsets[i], charsets[i + off], 0, &norm);
75 # if (ret != 0)
86 # for (i = 0; i < ncharset; ++i)
96 # for (i = 0; i < ncharset; i += 2) {
98 # if (ret == 0) {
101 # if (ret == 0 && tmp == src)
105 # return 0;
[all …]
H A DUCS@BMP%GB18030.src30 SRC_ZONE 0x0080-0xFFFD
32 DST_INVALID 0xFFFFFFFF
36 0x0080 = 0x81308130
37 0x0081 = 0x81308131
38 0x0082 = 0x81308132
39 0x0083 = 0x81308133
40 0x0084 = 0x81308134
41 0x0085 = 0x81308135
42 0x0086 = 0x81308136
43 0x0087 = 0x81308137
[all …]
/freebsd/tools/tools/locale/etc/charmaps/
H A DGB18030.TXT5 0x03 0x0003
6 0x04 0x0004
7 0x05 0x0005
8 0x06 0x0006
9 0x07 0x0007
10 0x08 0x0008
11 0x09 0x0009
12 0x0A 0x000A
13 0x0B 0x000B
14 0x0C 0x000C
[all …]
/freebsd/share/i18n/csmapper/ISO-8859/
H A DUCS%ISO-8859-2.src5 SRC_ZONE 0x0000-0xFFFF
7 DST_INVALID 0x100
44 # Column #1 is the ISO/IEC 8859-2 code (in hex as 0xXX)
45 # Column #2 is the Unicode (in hex as 0xXXXX)
61 0x0000-0x007F = 0x00-
62 0x0080 = 0x80
63 0x0081 = 0x81
64 0x0082 = 0x82
65 0x0083 = 0x83
66 0x0084 = 0x84
[all …]
H A DUCS%ISO-8859-3.src5 SRC_ZONE 0x0000-0xFFFF
7 DST_INVALID 0x100
44 # Column #1 is the ISO/IEC 8859-3 code (in hex as 0xXX)
45 # Column #2 is the Unicode (in hex as 0xXXXX)
61 0x0000-0x007F = 0x00-
62 0x0080 = 0x80
63 0x0081 = 0x81
64 0x0082 = 0x82
65 0x0083 = 0x83
66 0x0084 = 0x84
[all …]

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