Searched +full:0 +full:x020c8000 (Results 1 – 8 of 8) sorted by relevance
63 const: 086 reg = <0x021bc000 0x4000>;90 reg = <0x38 4>;94 reg = <0x20 4>;100 reg = <0x020c8000 0x1000>;101 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,102 <0 54 IRQ_TYPE_LEVEL_HIGH>,103 <0 127 IRQ_TYPE_LEVEL_HIGH>;112 #thermal-sensor-cells = <0>;
65 reg = <0x020c8000 0x1000>;75 anatop-reg-offset = <0x120>;78 anatop-min-bit-val = <0>;81 anatop-enable-bit = <0>;90 anatop-reg-offset = <0x140>;91 anatop-vol-bit-shift = <0>;93 anatop-delay-reg-offset = <0x170>;107 anatop-reg-offset = <0x140>;110 anatop-delay-reg-offset = <0x170>;126 #thermal-sensor-cells = <0>;
21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)35 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]41 * IO 0x00200000+0x100000 -> 0xf4000000+0x10000043 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x10000044 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x10000045 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x00400047 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x10000048 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x10000049 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x10000051 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000[all …]
47 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;82 #clock-cells = <0>;89 #clock-cells = <0>;96 #clock-cells = <0>;97 clock-frequency = <0>;103 #clock-cells = <0>;104 clock-frequency = <0>;117 reg = <0x00900000 0x20000>;[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0x0>;86 #clock-cells = <0>;92 #clock-cells = <0>;100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;105 #phy-cells = <0>;117 reg = <0x00900000 0x20000>;118 ranges = <0 0x00900000 0x20000>;128 reg = <0x00a01000 0x1000>,[all …]
58 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;108 #clock-cells = <0>;115 #clock-cells = <0>;122 #clock-cells = <0>;123 clock-frequency = <0>;129 #clock-cells = <0>;130 clock-frequency = <0>;149 reg = <0x00900000 0x20000>;[all …]
59 #clock-cells = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;71 #clock-cells = <0>;78 #size-cells = <0>;83 lvds-channel@0 {85 #size-cells = <0>;86 reg = <0>;89 port@0 {90 reg = <0>;[all …]
61 #size-cells = <0>;63 cpu0: cpu@0 {66 reg = <0>;100 #clock-cells = <0>;107 #clock-cells = <0>;114 #clock-cells = <0>;115 clock-frequency = <0>;121 #clock-cells = <0>;122 clock-frequency = <0>;128 #clock-cells = <0>;[all …]