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/linux/Documentation/devicetree/bindings/timer/
H A Dnvidia,tegra186-timer.yaml45 One per each timer channels 0 through 9.
57 One per each timer channels 0 through 15.
73 reg = <0x03010000 0x000e0000>;
74 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 reg = <0x02080000 0x00121000>;
93 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
/linux/lib/crypto/
H A Ddes.c30 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
31 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
32 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
33 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
34 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
35 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
36 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
37 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
38 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
39 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux/arch/powerpc/boot/dts/
H A Dfsp2.dts19 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x0>;
35 clock-frequency = <0>; /* Filled in by cuboot */
36 timebase-frequency = <0>; /* Filled in by cuboot */
48 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by
55 #clock-cells = <0>;
62 #address-cells = <0>;
63 #size-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi31 bus@0 {
36 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
40 reg = <0x0 0x00100000 0x0 0xf000>,
41 <0x0 0x0010f000 0x0 0x1000>;
47 reg = <0x0 0x02080000 0x0 0x00121000>;
48 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
70 reg = <0x0 0x02200000 0x0 0x10000>,
71 <0x0 0x02210000 0x0 0x10000>;
124 gpio-ranges = <&pinmux 0 0 164>;
129 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da6xx.xml30 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
68 <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
87 <reg64 offset="0x0800" name="CP_RB_BASE"/>
88 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
89 <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
90 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
91 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
92 <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
93 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
94 <bitfield name="IFPC" pos="0" type="boolean"/>
[all …]