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/linux/drivers/misc/
H A Dhi6421v600-irq.c31 OTMP = 0,
54 #define HISI_POWERKEY_IRQ_NUM 0
64 #define SOC_PMIC_IRQ_MASK_0_ADDR 0x0202
65 #define SOC_PMIC_IRQ0_ADDR 0x0212
73 * OTMP 0x0202 0x212 bit 0
74 * VBUS_CONNECT 0x0202 0x212 bit 1
75 * VBUS_DISCONNECT 0x0202 0x212 bit 2
76 * ALARMON_R 0x0202 0x212 bit 3
77 * HOLD_6S 0x0202 0x212 bit 4
78 * HOLD_1S 0x0202 0x212 bit 5
[all …]
/linux/include/video/
H A Dtgafb.h20 #define TGA_TYPE_8PLANE 0
28 #define TGA_ROM_OFFSET 0x0000000
29 #define TGA_REGS_OFFSET 0x0100000
30 #define TGA_8PLANE_FB_OFFSET 0x0200000
31 #define TGA_24PLANE_FB_OFFSET 0x0804000
32 #define TGA_24PLUSZ_FB_OFFSET 0x1004000
34 #define TGA_FOREGROUND_REG 0x0020
35 #define TGA_BACKGROUND_REG 0x0024
36 #define TGA_PLANEMASK_REG 0x0028
37 #define TGA_PIXELMASK_ONESHOT_REG 0x002c
[all …]
/linux/arch/xtensa/include/uapi/asm/
H A Dptrace.h19 #define REG_A_BASE 0x0000
20 #define REG_AR_BASE 0x0100
21 #define REG_PC 0x0020
22 #define REG_PS 0x02e6
23 #define REG_WB 0x0248
24 #define REG_WS 0x0249
25 #define REG_LBEG 0x0200
26 #define REG_LEND 0x0201
27 #define REG_LCOUNT 0x0202
28 #define REG_SAR 0x0203
[all …]
/linux/block/
H A Dopal_proto.h20 TCG_SECP_00 = 0,
30 OPAL_DTA_TOKENID_BYTESTRING = 0xe0,
31 OPAL_DTA_TOKENID_SINT = 0xe1,
32 OPAL_DTA_TOKENID_UINT = 0xe2,
33 OPAL_DTA_TOKENID_TOKEN = 0xe3, /* actual token is returned */
34 OPAL_DTA_TOKENID_INVALID = 0X0
37 #define DTAERROR_NO_METHOD_STATUS 0x89
38 #define GENERIC_HOST_SESSION_NUM 0x41
41 #define TPER_SYNC_SUPPORTED 0x01
43 #define LOCKING_SUPPORTED_MASK 0x01
[all …]
/linux/Documentation/arch/arm/
H A Dnetwinder.rst15 0x0000 0x000f DMA1
16 0x0020 0x0021 PIC1
17 0x0060 0x006f Keyboard
18 0x0070 0x007f RTC
19 0x0080 0x0087 DMA1
20 0x0088 0x008f DMA2
21 0x00a0 0x00a3 PIC2
22 0x00c0 0x00df DMA2
23 0x0180 0x0187 IRDA
24 0x01f0 0x01f6 ide0
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-avermedia-m135a.c23 { 0x0200, KEY_POWER2 },
24 { 0x022e, KEY_DOT }, /* '.' */
25 { 0x0201, KEY_MODE }, /* TV/FM or SOURCE */
27 { 0x0205, KEY_NUMERIC_1 },
28 { 0x0206, KEY_NUMERIC_2 },
29 { 0x0207, KEY_NUMERIC_3 },
30 { 0x0209, KEY_NUMERIC_4 },
31 { 0x020a, KEY_NUMERIC_5 },
32 { 0x020b, KEY_NUMERIC_6 },
33 { 0x020d, KEY_NUMERIC_7 },
[all …]
/linux/drivers/net/wireless/intersil/p54/
H A Deeprom.h131 /* common and choice range (0x0000 - 0x0fff) */
132 #define PDR_END 0x0000
133 #define PDR_MANUFACTURING_PART_NUMBER 0x0001
134 #define PDR_PDA_VERSION 0x0002
135 #define PDR_NIC_SERIAL_NUMBER 0x0003
136 #define PDR_NIC_RAM_SIZE 0x0005
137 #define PDR_RFMODEM_SUP_RANGE 0x0006
138 #define PDR_PRISM_MAC_SUP_RANGE 0x0007
139 #define PDR_NIC_ID 0x0008
141 #define PDR_MAC_ADDRESS 0x0101
[all …]
/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
/linux/sound/soc/codecs/
H A Dsi476x.c24 SI476X_DIGITAL_IO_OUTPUT_FORMAT = 0x0203,
25 SI476X_DIGITAL_IO_OUTPUT_SAMPLE_RATE = 0x0202,
33 #define SI476X_DIGITAL_IO_OUTPUT_WIDTH_MASK ((0x7 << SI476X_DIGITAL_IO_SLOT_SIZE_SHIFT) | \
34 (0x7 << SI476X_DIGITAL_IO_SAMPLE_SIZE_SHIFT))
35 #define SI476X_DIGITAL_IO_OUTPUT_FORMAT_MASK (0x7e)
38 SI476X_DAUDIO_MODE_I2S = (0x0 << 1),
39 SI476X_DAUDIO_MODE_DSP_A = (0x6 << 1),
40 SI476X_DAUDIO_MODE_DSP_B = (0x7 << 1),
41 SI476X_DAUDIO_MODE_LEFT_J = (0x8 << 1),
42 SI476X_DAUDIO_MODE_RIGHT_J = (0x9 << 1),
[all …]
H A Drt1308-sdw.h12 { 0x0000, 0x00 },
13 { 0x0001, 0x00 },
14 { 0x0002, 0x00 },
15 { 0x0003, 0x00 },
16 { 0x0004, 0x00 },
17 { 0x0005, 0x01 },
18 { 0x0020, 0x00 },
19 { 0x0022, 0x00 },
20 { 0x0023, 0x00 },
21 { 0x0024, 0x00 },
[all …]
H A Drt711-sdw.h12 { 0x0000, 0x00 },
13 { 0x0001, 0x00 },
14 { 0x0002, 0x00 },
15 { 0x0003, 0x00 },
16 { 0x0004, 0x00 },
17 { 0x0005, 0x01 },
18 { 0x0020, 0x00 },
19 { 0x0022, 0x00 },
20 { 0x0023, 0x00 },
21 { 0x0024, 0x00 },
[all …]
H A Drt715-sdw.h12 { 0x0000, 0x00 },
13 { 0x0001, 0x00 },
14 { 0x0002, 0x00 },
15 { 0x0003, 0x00 },
16 { 0x0004, 0x00 },
17 { 0x0005, 0x01 },
18 { 0x0020, 0x00 },
19 { 0x0022, 0x00 },
20 { 0x0023, 0x00 },
21 { 0x0024, 0x00 },
[all …]
H A Drt700-sdw.h12 { 0x0000, 0x0000 },
13 { 0x0001, 0x0000 },
14 { 0x0002, 0x0000 },
15 { 0x0003, 0x0000 },
16 { 0x0004, 0x0000 },
17 { 0x0005, 0x0001 },
18 { 0x0020, 0x0000 },
19 { 0x0022, 0x0000 },
20 { 0x0023, 0x0000 },
21 { 0x0024, 0x0000 },
[all …]
/linux/drivers/ata/
H A Dpata_triflex.c46 { 0x80, 1, 0x01, 0x01 }, in triflex_prereset()
47 { 0x80, 1, 0x02, 0x02 } in triflex_prereset()
76 u32 timing = 0; in triflex_load_timing()
78 int channel_offset = ap->port_no ? 0x74: 0x70; in triflex_load_timing()
79 unsigned int is_slave = (adev->devno != 0); in triflex_load_timing()
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
[all …]
/linux/include/uapi/linux/
H A Dif_pppox.h60 #define PX_PROTO_OE 0 /* Currently just PPPoE */
112 #define PPPOEIOCSFWD _IOW(0xB1 ,0, size_t)
113 #define PPPOEIOCDFWD _IO(0xB1 ,1)
114 /*#define PPPOEIOCGFWD _IOWR(0xB1,2, size_t)*/
117 #define PADI_CODE 0x09
118 #define PADO_CODE 0x07
119 #define PADR_CODE 0x19
120 #define PADS_CODE 0x65
121 #define PADT_CODE 0xa7
129 #define PTT_EOL __cpu_to_be16(0x0000)
[all …]
/linux/arch/m68k/include/asm/
H A Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]
/linux/drivers/media/pci/saa7164/
H A Dsaa7164-types.h57 NONE = 0,
91 SET_CUR = 0x01,
92 GET_CUR = 0x81,
93 GET_MIN = 0x82,
94 GET_MAX = 0x83,
95 GET_RES = 0x84,
96 GET_LEN = 0x85,
97 GET_INFO = 0x86,
98 GET_DEF = 0x87
149 ITT_ANTENNA = 0x0203,
[all …]
/linux/drivers/regulator/
H A Dmt6380-regulator.c16 #define MT6380_ALDO_CON_0 0x0000
17 #define MT6380_BTLDO_CON_0 0x0004
18 #define MT6380_COMP_CON_0 0x0008
19 #define MT6380_CPUBUCK_CON_0 0x000C
20 #define MT6380_CPUBUCK_CON_1 0x0010
21 #define MT6380_CPUBUCK_CON_2 0x0014
22 #define MT6380_DDRLDO_CON_0 0x0018
23 #define MT6380_MLDO_CON_0 0x001C
24 #define MT6380_PALDO_CON_0 0x0020
25 #define MT6380_PHYLDO_CON_0 0x0024
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h27 // base address: 0x1fb00
28 …UVD_PGFSM_CONFIG 0x00c0
30 …UVD_PGFSM_STATUS 0x00c1
32 …UVD_POWER_STATUS 0x00c4
34 …CC_UVD_HARVESTING 0x00c7
36 …UVD_DPG_LMA_CTL 0x00d1
38 …UVD_DPG_LMA_DATA 0x00d2
40 …UVD_DPG_LMA_MASK 0x00d3
42 …UVD_DPG_PAUSE 0x00d4
44 …UVD_SCRATCH1 0x00d5
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dperf_event.c14 #define PPC_CCBR(idx) (0xff200800 + (sizeof(u32) * idx))
15 #define PPC_PMCTR(idx) (0xfc100000 + (sizeof(u32) * idx))
17 #define CCBR_CIT_MASK (0x7ff << 6)
20 #define CCBR_PPCE (1 << 0)
37 #define PPC_PMCAT 0xfc100240
39 #define PPC_PMCAT 0xfc100080
61 * 0x0000 number of elapsed cycles
62 * 0x0200 number of elapsed cycles in privileged mode
63 * 0x0280 number of elapsed cycles while SR.BL is asserted
64 * 0x0202 instruction execution
[all …]
/linux/drivers/iio/adc/
H A Dti-lmp92064.c24 #define TI_LMP92064_REG_CONFIG_A 0x0000
25 #define TI_LMP92064_REG_CONFIG_B 0x0001
26 #define TI_LMP92064_REG_CHIP_REV 0x0006
28 #define TI_LMP92064_REG_MFR_ID1 0x000C
29 #define TI_LMP92064_REG_MFR_ID2 0x000D
31 #define TI_LMP92064_REG_REG_UPDATE 0x000F
32 #define TI_LMP92064_REG_CONFIG_REG 0x0100
33 #define TI_LMP92064_REG_STATUS 0x0103
35 #define TI_LMP92064_REG_DATA_VOUT_LSB 0x0200
36 #define TI_LMP92064_REG_DATA_VOUT_MSB 0x0201
[all …]
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_adminq_cmd.h15 #define IAVF_FW_API_VERSION_MAJOR 0x0001
16 #define IAVF_FW_API_VERSION_MINOR_X722 0x0005
17 #define IAVF_FW_API_VERSION_MINOR_X710 0x0008
24 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
29 iavf_aqc_opc_get_version = 0x0001,
30 iavf_aqc_opc_driver_version = 0x0002,
31 iavf_aqc_opc_queue_shutdown = 0x0003,
32 iavf_aqc_opc_set_pf_context = 0x0004,
35 iavf_aqc_opc_request_resource = 0x0008,
36 iavf_aqc_opc_release_resource = 0x0009,
[all …]
/linux/include/media/
H A Ddvb-usb-ids.h23 #define USB_VID_774 0x7a69
24 #define USB_VID_ADSTECH 0x06e1
25 #define USB_VID_AFATECH 0x15a4
26 #define USB_VID_ALCOR_MICRO 0x058f
27 #define USB_VID_ALINK 0x05e3
28 #define USB_VID_AME 0x06be
29 #define USB_VID_AMT 0x1c73
30 #define USB_VID_ANCHOR 0x0547
31 #define USB_VID_ANSONIC 0x10b9
32 #define USB_VID_ANUBIS_ELECTRONIC 0x10fd
[all …]
/linux/drivers/media/pci/ddbridge/
H A Dddbridge-main.c43 MODULE_PARM_DESC(msi, "Control MSI interrupts: 0-disable, 1-enable (default)");
45 MODULE_PARM_DESC(msi, "Control MSI interrupts: 0-disable (default), 1-enable");
55 ddbwritel(dev, 0, INTERRUPT_ENABLE); in ddb_irq_disable()
56 ddbwritel(dev, 0, MSI1_ENABLE); in ddb_irq_disable()
72 free_irq(pci_irq_vector(dev->pdev, 0), dev); in ddb_irq_exit()
117 ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); in ddb_irq_init()
118 ddbwritel(dev, 0x00000000, MSI1_ENABLE); in ddb_irq_init()
119 ddbwritel(dev, 0x00000000, MSI2_ENABLE); in ddb_irq_init()
120 ddbwritel(dev, 0x00000000, MSI3_ENABLE); in ddb_irq_init()
121 ddbwritel(dev, 0x00000000, MSI4_ENABLE); in ddb_irq_init()
[all …]
/linux/drivers/infiniband/hw/irdma/
H A Duser.h20 #define IRDMA_MAX_MR_SIZE 0x200000000000ULL
22 #define IRDMA_ACCESS_FLAGS_LOCALREAD 0x01
23 #define IRDMA_ACCESS_FLAGS_LOCALWRITE 0x02
24 #define IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04
25 #define IRDMA_ACCESS_FLAGS_REMOTEREAD 0x05
26 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08
27 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE 0x0a
28 #define IRDMA_ACCESS_FLAGS_BIND_WINDOW 0x10
29 #define IRDMA_ACCESS_FLAGS_ZERO_BASED 0x20
30 #define IRDMA_ACCESS_FLAGS_ALL 0x3f
[all …]

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