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/freebsd/contrib/ntp/sntp/libopts/
H A Dag-char-map.h51 #if 0 /* mapping specification source (from autogen.map) */
81 // oct-digit "0-7"
111 #endif /* 0 -- mapping spec. source */
116 #define IS_NEWLINE_CHAR( _c) is_ag_char_map_char((char)(_c), 0x00000001)
117 #define SPN_NEWLINE_CHARS(_s) spn_ag_char_map_chars(_s, 0)
118 #define BRK_NEWLINE_CHARS(_s) brk_ag_char_map_chars(_s, 0)
119 #define SPN_NEWLINE_BACK(s,e) spn_ag_char_map_back(s, e, 0)
120 #define BRK_NEWLINE_BACK(s,e) brk_ag_char_map_back(s, e, 0)
121 #define IS_NUL_BYTE_CHAR( _c) is_ag_char_map_char((char)(_c), 0x00000002)
126 #define IS_DIR_SEP_CHAR( _c) is_ag_char_map_char((char)(_c), 0x00000004)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dfsl,spdif.txt28 "rxtx<0-7>" Clock source list for tx and rx clock.
50 reg = <0x02004000 0x4000>;
51 interrupts = <0 52 0x04>;
52 dmas = <&sdma 14 18 0>,
53 <&sdma 15 18 0>;
58 <&clks 0>, <&clks 118>,
60 <&clks 0>;
H A Dfsl,spdif.yaml137 reg = <0x02004000 0x4000>;
138 interrupts = <0 52 0x04>;
139 dmas = <&sdma 14 18 0>,
140 <&sdma 15 18 0>;
144 <&clks 0>, <&clks 118>,
146 <&clks 0>;
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_osprey22_scoemu.ini92 { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 },
94 { 0x0000801c , 0x0e8d8013 , 0x0e8d8013 , 0x0e8d8013 , 0x0e8d8013 },
96 { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 },
102 { 0x0000a2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 },
103 { 0x0000a2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 },
104 { 0x0000a2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 },
105 { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 },
106 { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 },
107 { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 },
108 { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 },
[all …]
H A Dar9300_osprey22.ini80 { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 },
81 { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 },
86 { 0x0000a2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 },
87 { 0x0000a2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 },
88 { 0x0000a2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 },
89 { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 },
90 { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 },
91 { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 },
92 { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 },
93 { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sll.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
97 clock-frequency = <0>;
103 #clock-cells = <0>;
104 clock-frequency = <0>;
117 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6sl.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
86 #clock-cells = <0>;
92 #clock-cells = <0>;
100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
105 #phy-cells = <0>;
117 reg = <0x00900000 0x20000>;
118 ranges = <0 0x00900000 0x20000>;
128 reg = <0x00a01000 0x1000>,
[all …]
H A Dimx6qdl.dtsi59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
[all …]
H A Dimx6sx.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]