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30 #define AMD_WINDOW_MAXSIZE 0x0020000036 #define SC520_PAR_ADDR_MASK 0x00003fff41 #define SC520_PAR_SIZE_MASK 0x01ffc00051 #define SC520_PAR_BOOTCS 0x8a00000052 #define SC520_PAR_ROMCS1 0xaa00000053 #define SC520_PAR_ROMCS2 0xca000000 /* Cache disabled, 64K page */69 .size = 0,76 .offset = 0,77 .size = 0x000e000081 .offset = 0x00100000,[all …]