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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
H A Ddra7.dtsi61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0>;
109 opp-supported-hw = <0xFF 0x01>;
119 opp-supported-hw = <0xFF 0x02>;
[all …]
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dfsl,imx6q-pcie.txt22 - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
23 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
70 reg = <0x01ffc000 0x04000>,
71 <0x01f00000 0x80000>;
76 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
77 0x81000000 0 0 0x01f80000 0 0x00010000
78 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
83 interrupt-map-mask = <0 0 0 0x7>;
84 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
85 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfsl,imx6q-pcie.yaml212 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>;
218 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
220 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
225 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
227 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/socionext/
H A Duniphier-support-card.dtsi10 ranges = <1 0x00000000 0x42000000 0x02000000>;
14 reg = <1 0x01f00000 0x1000>;
22 reg = <1 0x01fb0000 0x20>;
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
H A Dlite5200b.dts22 gpios = <&gpt2 0 1>;
25 gpios = <&gpt3 0 1>;
34 memory@0 {
35 reg = <0x00000000 0x10000000>; // 256MB
41 cell-index = <0>;
87 phy0: ethernet-phy@0 {
88 reg = <0>;
95 reg = <0x50>;
101 reg = <0x8000 0x4000>;
106 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
H A Diss4xx-mpic.dts17 /memreserve/ 0x01f00000 0x00100000;
24 dcr-parent = <&{/cpus/cpu@0}>;
32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
62 cpu-release-addr = <0 0x01f00100>;
78 cpu-release-addr = <0 0x01f00200>;
94 cpu-release-addr = <0 0x01f00300>;
100 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
107 dcr-reg = <0xffc00000 0x00030000>;
[all …]
H A Dakebono.dts14 /memreserve/ 0x01f00000 0x00100000; // spin table
21 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
59 cpu-release-addr = <0x0 0x01f00000>;
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
[all …]
H A Deiger.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
56 cell-index = <0>;
57 dcr-reg = <0x0c0 0x009>;
58 #address-cells = <0>;
[all …]
/freebsd/sys/dev/e1000/
H A De1000_82571.h38 #define ID_LED_RESERVED_F746 0xF746
44 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
48 #define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n)))
50 #define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
51 #define E1000_EIAC_MASK_82574 0x01F00000
53 #define E1000_IVAR_INT_ALLOC_VALID 0x8
56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000
59 #define E1000_IDLE_ERROR_COUNT_MASK 0xFF
61 #define E1000_RECEIVE_ERROR_MAX 0xFFFF
/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dallwinner,sun6i-a31-rtc.yaml42 - description: RTC Alarm 0
58 - the Low Frequency Oscillator or LOSC, at index 0,
188 reg = <0x01f00000 0x400>;
189 interrupts = <0 40 4>, <0 41 4>;
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp1020utm-pc.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x2000000>;
44 partition@0 {
46 reg = <0x0 0x00040000>;
52 reg = <0x00040000 0x003c0000>;
58 reg = <0x00400000 0x01b00000>;
66 reg = <0x01f00000 0x00100000>;
77 reg = <0x68>;
82 phy0: ethernet-phy@0 {
83 interrupts = <3 1 0 0>;
[all …]
H A Dp1010rdb.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x2000000>;
46 reg = <0x00040000 0x00040000>;
52 reg = <0x00080000 0x00700000>;
58 reg = <0x00800000 0x01400000>;
66 reg = <0x01f00000 0x00100000>;
72 ifc_nand: nand@1,0 {
76 reg = <0x1 0x0 0x10000>;
79 cpld@3,0 {
83 reg = <0x3 0x0 0x0000020>;
[all …]
H A Dp1021mds.dts23 reg = <0x0 0xffe05000 0x0 0x1000>;
26 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
27 0x1 0x0 0x0 0xf8000000 0x00008000
28 0x2 0x0 0x0 0xf8010000 0x00020000
29 0x3 0x0 0x0 0xf8020000 0x00020000>;
31 nand@0,0 {
36 reg = <0x0 0x0 0x40000>;
38 partition@0 {
41 reg = <0x0 0x00100000>;
48 reg = <0x00100000 0x00100000>;
[all …]
H A Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
39 nor@0,0 {
43 reg = <0x0 0x0 0x02000000>;
46 partition@0 {
[all …]
/freebsd/sys/dev/cxgbe/firmware/
H A Dt6fw_cfg_hashfilter.txt19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
32 # TP number of RX channels (0 = auto)
33 tp_nrxch = 0
38 # TP number of TX channels (0 = auto)
39 tp_ntxch = 0
45 reg[0x7d04] = 0x00010008/0x00010008
48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
54 reg[0x7d4c] = 0x00010000/0x00010000 # set DisableNewPshFlag
[all …]
H A Dt6fw_cfg.txt19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
32 # TP number of RX channels (0 = auto)
33 tp_nrxch = 0
38 # TP number of TX channels (0 = auto)
39 tp_ntxch = 0
45 reg[0x7d04] = 0x00012008/0x00012008
48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
54 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
[all …]
H A Dt6fw_cfg_fpga.txt34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
82 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm47094-linksys-panamera.dts19 memory@0 {
21 reg = <0x00000000 0x08000000>,
22 <0x88000000 0x08000000>;
27 reg = <0x1c080000 0x100000>;
83 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
136 reg = <0x200>;
138 #size-cells = <0>;
[all...]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212desc.h32 uint32_t ds_ctl0; /* DMA control 0 */
38 uint32_t status0;/* DMA status 0 */
42 uint32_t status0;/* DMA status 0 */
58 #define AR_FrameLen 0x00000fff /* frame length */
60 #define AR_XmitPower 0x003f0000 /* transmit power control */
62 #define AR_RTSCTSEnable 0x00400000 /* RTS/CTS protocol enable */
63 #define AR_VEOL 0x00800000 /* virtual end-of-list */
64 #define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
65 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */
67 #define AR_TxInterReq 0x20000000 /* TX interrupt request */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3798cv200.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x0 0x0>;
34 d-cache-size = <0x8000>; /* 32 KiB */
37 i-cache-size = <0x8000>; /* 32 KiB */
46 reg = <0x0 0x1>;
48 d-cache-size = <0x8000>; /* 32 KiB */
51 i-cache-size = <0x8000>; /* 32 KiB */
60 reg = <0x0 0x2>;
62 d-cache-size = <0x8000>; /* 32 KiB */
[all …]

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