Searched +full:0 +full:x01c20000 (Results 1 – 14 of 14) sorted by relevance
17 const: 046 #clock-cells = <0>;48 reg = <0x01c20000 0x4>;55 #clock-cells = <0>;57 reg = <0x01c20000 0x4>;64 #clock-cells = <0>;66 reg = <0x01c20000 0x4>;
136 reg = <0x01c20000 0x400>;146 reg = <0x01f01400 0x100>;
33 #define DA8XX_CP_INTC_BASE 0xfffee00037 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)39 #define DA8XX_JTAG_ID_REG 0x1840 #define DA8XX_HOST1CFG_REG 0x4441 #define DA8XX_CHIPSIG_REG 0x17442 #define DA8XX_CFGCHIP0_REG 0x17c43 #define DA8XX_CFGCHIP1_REG 0x18044 #define DA8XX_CFGCHIP2_REG 0x18445 #define DA8XX_CFGCHIP3_REG 0x18846 #define DA8XX_CFGCHIP4_REG 0x18c[all …]
17 #clock-cells = <0>;24 #clock-cells = <0>;33 #size-cells = <0>;35 cpu@0 {38 reg = <0x0>;51 reg = <0x01c00000 0x30>;58 reg = <0x00010000 0x1000>;61 ranges = <0 0x00010000 0x1000>;63 otg_sram: sram-section@0 {66 reg = <0x0000 0x1000>;[all …]
72 #size-cells = <0>;74 cpu@0 {77 reg = <0>;102 #clock-cells = <0>;110 #clock-cells = <0>;126 reg = <0x01000000 0x10000>;138 reg = <0x01100000 0x100000>;139 clocks = <&display_clocks 0>,143 resets = <&display_clocks 0>;147 #size-cells = <0>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
91 #size-cells = <0>;93 cpu0: cpu@0 {96 reg = <0>;112 #clock-cells = <0>;120 #clock-cells = <0>;136 reg = <0x01c00000 0x30>;143 reg = <0x01d00000 0x80000>;146 ranges = <0 0x01d00000 0x80000>;148 ve_sram: sram-section@0 {151 reg = <0x000000 0x80000>;[all …]
87 #clock-cells = <0>;95 #clock-cells = <0>;118 reg = <0x01000000 0x10000>;129 compatible = "allwinner,sun8i-h3-de2-mixer-0";130 reg = <0x01100000 0x100000>;139 #size-cells = <0>;153 reg = <0x01c02000 0x1000>;163 reg = <0x01c0c000 0x1000>;172 #size-cells = <0>;174 tcon0_in: port@0 {[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
62 #size-cells = <0>;64 cpu0: cpu@0 {71 reg = <0>;115 reg = <0x100>;126 reg = <0x101>;137 reg = <0x102>;148 reg = <0x103>;168 #clock-cells = <0>;181 #clock-cells = <0>;188 #clock-cells = <0>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;213 #clock-cells = <0>;221 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;252 #clock-cells = <0>;254 reg = <0x01c200d0 0x4>;274 reg = <0x01c02000 0x1000>;[all …]
64 #clock-cells = <0>;72 #clock-cells = <0>;82 #size-cells = <0>;84 cpu0: cpu@0 {87 reg = <0>;130 polling-delay-passive = <0>;131 polling-delay = <0>;132 thermal-sensors = <&ths 0>;143 hysteresis = <0>;161 polling-delay-passive = <0>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]
33 #clock-cells = <0>;38 #clock-cells = <0>;45 #size-cells = <0>;47 CPU0: cpu@0 {50 reg = <0x0 0x0>;51 clocks = <&cpufreq_hw 0>;58 qcom,freq-domain = <&cpufreq_hw 0>;78 reg = <0x0 0x100>;79 clocks = <&cpufreq_hw 0>;86 qcom,freq-domain = <&cpufreq_hw 0>;[all …]