Home
last modified time | relevance | path

Searched +full:0 +full:x01c17000 (Results 1 – 9 of 9) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dallwinner,sun6i-a31-msgbox.yaml52 description: first cell is the channel number (0-7)
73 reg = <0x01c17000 0x1000>;
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
H A Dsunxi-h3-h5.dtsi87 #clock-cells = <0>;
95 #clock-cells = <0>;
118 reg = <0x01000000 0x10000>;
129 compatible = "allwinner,sun8i-h3-de2-mixer-0";
130 reg = <0x01100000 0x100000>;
139 #size-cells = <0>;
153 reg = <0x01c02000 0x1000>;
163 reg = <0x01c0c000 0x1000>;
172 #size-cells = <0>;
174 tcon0_in: port@0 {
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
H A Dsun8i-r40.dtsi64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
[all...]
H A Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
181 size = <0x6000000>;
182 alloc-ranges = <0x40000000 0x10000000>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a64.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
74 i-cache-size = <0x8000>;
77 d-cache-size = <0x8000>;
91 i-cache-size = <0x8000>;
94 d-cache-size = <0x8000>;
108 i-cache-size = <0x8000>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]