Home
last modified time | relevance | path

Searched +full:0 +full:x01c08000 (Results 1 – 13 of 13) sorted by relevance

/linux/arch/arm/mach-davinci/
H A Ddevices-da8xx.c27 #define DA8XX_TPCC_BASE 0x01c00000
28 #define DA8XX_TPTC0_BASE 0x01c08000
29 #define DA8XX_TPTC1_BASE 0x01c08400
30 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
31 #define DA8XX_I2C0_BASE 0x01c22000
32 #define DA8XX_RTC_BASE 0x01c23000
33 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
34 #define DA8XX_MMCSD0_BASE 0x01c40000
35 #define DA8XX_SPI0_BASE 0x01c41000
36 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8450.dtsi40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc8180x.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
62 clocks = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
91 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dtalos.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0x0 0x0>;
41 clocks = <&cpufreq_hw 0>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
60 reg = <0x0 0x100>;
67 clocks = <&cpufreq_hw 0>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
85 reg = <0x0 0x200>;
92 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8280xp.dtsi34 #clock-cells = <0>;
39 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #size-cells = <0>;
69 cpu0: cpu@0 {
72 reg = <0 0>;
73 clocks = <&cpufreq_hw 0>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0 0x100>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 cpu0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]
H A Dkodiak.dtsi84 #clock-cells = <0>;
90 #clock-cells = <0>;
101 reg = <0x0 0x004cd000 0x0 0x1000>;
105 reg = <0x0 0x80000000 0x0 0x600000>;
110 reg = <0x0 0x80600000 0x0 0x200000>;
115 reg = <0x0 0x80800000 0x0 0x60000>;
120 reg = <0x0 0x80860000 0x0 0x20000>;
126 reg = <0x0 0x80884000 0x0 0x10000>;
131 reg = <0x0 0x808ff000 0x0 0x1000>;
136 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
78 clocks = <&cpufreq_hw 0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0 0x100>;
[all …]
H A Dhamoa.dtsi38 #clock-cells = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
58 #clock-cells = <0>;
68 #size-cells = <0>;
70 cpu0: cpu@0 {
73 reg = <0x0 0x0>;
76 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
89 reg = <0x0 0x100>;
92 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
[all …]