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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie-x1e80100.yaml91 reg = <0 0x01c08000 0 0x3000>,
92 <0 0x7c000000 0 0xf1d>,
93 <0 0x7c000f40 0 0xa8>,
94 <0 0x7c001000 0 0x1000>,
95 <0 0x7c100000 0 0x100000>,
96 <0 0x01c0b000 0 0x1000>;
98 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
99 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
101 bus-range = <0x00 0xff>;
103 linux,pci-domain = <0>;
[all …]
H A Dqcom,pcie-sc7280.yaml95 reg = <0 0x01c08000 0 0x3000>,
96 <0 0x40000000 0 0xf1d>,
97 <0 0x40000f20 0 0xa8>,
98 <0 0x40001000 0 0x1000>,
99 <0 0x40100000 0 0x100000>;
101 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
102 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
104 bus-range = <0x00 0xff>;
156 interrupt-map-mask = <0 0 0 0x7>;
157 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc8180x.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
59 clocks = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi38 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
58 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi34 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #size-cells = <0>;
67 CPU0: cpu@0 {
70 reg = <0 0>;
71 clocks = <&cpufreq_hw 0>;
76 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0 0x100>;
[all …]
H A Dsm8450.dtsi39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi78 #clock-cells = <0>;
85 #clock-cells = <0>;
92 #size-cells = <0>;
94 CPU0: cpu@0 {
97 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
126 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw 0>;
131 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8650.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
59 #clock-cells = <0>;
69 #size-cells = <0>;
71 CPU0: cpu@0 {
74 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0 0x100>;
[all …]
H A Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 CPU0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]
H A Dsm8250.dtsi80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 CPU0: cpu@0 {
99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 0>;
107 qcom,freq-domain = <&cpufreq_hw 0>;
109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
115 cache-size = <0x20000>;
121 cache-size = <0x400000>;
[all …]
H A Dsc7280.dtsi81 #clock-cells = <0>;
87 #clock-cells = <0>;
98 reg = <0x0 0x004cd000 0x0 0x1000>;
102 reg = <0x0 0x80000000 0x0 0x600000>;
107 reg = <0x0 0x80600000 0x0 0x200000>;
112 reg = <0x0 0x80800000 0x0 0x60000>;
117 reg = <0x0 0x80860000 0x0 0x20000>;
123 reg = <0x0 0x80884000 0x0 0x10000>;
128 reg = <0x0 0x808ff000 0x0 0x1000>;
133 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]