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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
H A Dnbio_2_3_offset.h27 // base address: 0x0
28 …BIF_BX_PF_MM_INDEX 0x0000
29 …ne mmBIF_BX_PF_MM_INDEX_BASE_IDX 0
30 …BIF_BX_PF_MM_DATA 0x0001
31 …ne mmBIF_BX_PF_MM_DATA_BASE_IDX 0
32 …BIF_BX_PF_MM_INDEX_HI 0x0006
33 …ne mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 0
37 // base address: 0x0
38 …SYSHUB_INDEX_OVLP 0x0008
39 …ne mmSYSHUB_INDEX_OVLP_BASE_IDX 0
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx8ulp-pinctrl.yaml73 reg = <0x298c0000 0x10000>;
77 <0x0138 0x08F0 0x4 0x3 0x3>,
78 <0x013C 0x08EC 0x4 0x3 0x3>;
/linux/drivers/media/platform/chips-media/wave5/
H A Dwave5-regdefine.h12 W5_INIT_VPU = 0x0001,
13 W5_WAKEUP_VPU = 0x0002,
14 W5_SLEEP_VPU = 0x0004,
15 W5_CREATE_INSTANCE = 0x0008, /* queuing command */
16 W5_FLUSH_INSTANCE = 0x0010,
17 W5_DESTROY_INSTANCE = 0x0020, /* queuing command */
18 W5_INIT_SEQ = 0x0040, /* queuing command */
19 W5_SET_FB = 0x0080,
20 W5_DEC_ENC_PIC = 0x0100, /* queuing command */
21 W5_ENC_SET_PARAM = 0x0200, /* queuing command */
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux/drivers/media/cec/platform/s5p/
H A Dregs-cec.h16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-evm-icssg1-dualemac.dtso24 #size-cells = <0>;
26 mdio@0 {
27 reg = <0x0>;
29 #size-cells = <0>;
43 AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
44 AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
45 AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
46 AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
47 AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
48 AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
[all …]
H A Dk3-am642-evm-icssg1-dualemac-mii.dtso23 #size-cells = <0>;
25 mdio@0 {
26 reg = <0x0>;
28 #size-cells = <0>;
40 AM64X_IOPAD(0x00f8, PIN_INPUT, 1) /* (V9) PRG1_PRU0_GPO16.PR1_MII_MT0_CLK */
41 AM64X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y9) PRG1_PRU0_GPO15.PR1_MII0_TXEN */
42 AM64X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA9) PRG1_PRU0_GPO14.PR1_MII0_TXD3 */
43 AM64X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (W9) PRG1_PRU0_GPO13.PR1_MII0_TXD2 */
44 AM64X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (U9) PRG1_PRU0_GPO12.PR1_MII0_TXD1 */
45 AM64X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA8) PRG1_PRU0_GPO11.PR1_MII0_TXD0 */
[all …]
/linux/sound/soc/sof/mediatek/mt8186/
H A Dmt8186.h23 #define ADSP_CFGREG_SW_RSTN 0x0000
24 #define SW_DBG_RSTN_C0 BIT(0)
26 #define ADSP_HIFI_IO_CONFIG 0x000C
29 #define ADSP_IRQ_MASK 0x0030
30 #define ADSP_DVFSRC_REQ 0x0040
31 #define ADSP_DDREN_REQ_0 0x0044
32 #define ADSP_SEMAPHORE 0x0064
33 #define ADSP_WDT_CON_C0 0x007C
34 #define ADSP_MBOX_IRQ_EN 0x009C
35 #define DSP_MBOX0_IRQ_EN BIT(0)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dsdio.h12 #define MCR_WCIR 0x0000
13 #define MCR_WHLPCR 0x0004
18 #define WHLPCR_INT_EN_SET BIT(0)
20 #define MCR_WSDIOCSR 0x0008
21 #define MCR_WHCR 0x000C
32 #define MCR_WHISR 0x0010
33 #define MCR_WHIER 0x0014
40 #define WHIER_TX_DONE_INT_EN BIT(0)
47 #define MCR_WASR 0x0020
48 #define MCR_WSICR 0x0024
[all …]
/linux/include/linux/platform_data/
H A Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/linux/drivers/thermal/qcom/
H A Dtsens-v2.c12 #define SROT_HW_VER_OFF 0x0000
13 #define SROT_CTRL_OFF 0x0004
16 #define TM_INT_EN_OFF 0x0004
17 #define TM_UPPER_LOWER_INT_STATUS_OFF 0x0008
18 #define TM_UPPER_LOWER_INT_CLEAR_OFF 0x000c
19 #define TM_UPPER_LOWER_INT_MASK_OFF 0x0010
20 #define TM_CRITICAL_INT_STATUS_OFF 0x0014
21 #define TM_CRITICAL_INT_CLEAR_OFF 0x0018
22 #define TM_CRITICAL_INT_MASK_OFF 0x001c
23 #define TM_Sn_UPPER_LOWER_THRESHOLD_OFF 0x0020
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_3_1_offset.h28 // base address: 0x0
29 …IRQ_BRIDGE_CNTL 0x003e
33 // base address: 0x0
34 …BIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000
35 …BIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002
36 …BIF_CFG_DEV0_EPF0_COMMAND 0x0004
37 …BIF_CFG_DEV0_EPF0_STATUS 0x0006
38 …BIF_CFG_DEV0_EPF0_REVISION_ID 0x0008
39 …BIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009
40 …BIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_5_0_0_offset.h27 // base address: 0x3c80
28 …HDP_MMHUB_TLVL 0x0000
29 …ne mmHDP_MMHUB_TLVL_BASE_IDX 0
30 …HDP_MMHUB_UNITID 0x0001
31 …ne mmHDP_MMHUB_UNITID_BASE_IDX 0
32 …HDP_NONSURFACE_BASE 0x0040
33 …ne mmHDP_NONSURFACE_BASE_BASE_IDX 0
34 …HDP_NONSURFACE_INFO 0x0041
35 …ne mmHDP_NONSURFACE_INFO_BASE_IDX 0
36 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_7_0_0_offset.h29 // base address: 0x3c80
30 …HDP_MMHUB_TLVL 0x0008
31 …e regHDP_MMHUB_TLVL_BASE_IDX 0
32 …HDP_MMHUB_UNITID 0x0009
33 …e regHDP_MMHUB_UNITID_BASE_IDX 0
34 …HDP_NONSURFACE_BASE 0x0040
35 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
36 …HDP_NONSURFACE_INFO 0x0041
37 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
38 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_4_4_2_offset.h29 // base address: 0x3c80
30 …HDP_MMHUB_TLVL 0x0000
31 …e regHDP_MMHUB_TLVL_BASE_IDX 0
32 …HDP_MMHUB_UNITID 0x0001
33 …e regHDP_MMHUB_UNITID_BASE_IDX 0
34 …HDP_NONSURFACE_BASE 0x0040
35 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
36 …HDP_NONSURFACE_INFO 0x0041
37 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
38 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_5_2_1_offset.h29 // base address: 0x3c80
30 …HDP_MMHUB_TLVL 0x0000
31 …e regHDP_MMHUB_TLVL_BASE_IDX 0
32 …HDP_MMHUB_UNITID 0x0001
33 …e regHDP_MMHUB_UNITID_BASE_IDX 0
34 …HDP_NONSURFACE_BASE 0x0040
35 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
36 …HDP_NONSURFACE_INFO 0x0041
37 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
38 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_4_0_offset.h27 // base address: 0x3c80
28 #define mmHDP_MMHUB_TLVL 0x0000
29 #define mmHDP_MMHUB_TLVL_BASE_IDX 0
30 #define mmHDP_MMHUB_UNITID 0x0001
31 #define mmHDP_MMHUB_UNITID_BASE_IDX 0
32 #define mmHDP_NONSURFACE_BASE 0x0040
33 #define mmHDP_NONSURFACE_BASE_BASE_IDX 0
34 #define mmHDP_NONSURFACE_INFO 0x0041
35 #define mmHDP_NONSURFACE_INFO_BASE_IDX 0
36 #define mmHDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_6_0_0_offset.h29 // base address: 0x3c80
30 …HDP_NONSURFACE_BASE 0x0040
31 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
32 …HDP_NONSURFACE_INFO 0x0041
33 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
34 …HDP_NONSURFACE_BASE_HI 0x0042
35 …e regHDP_NONSURFACE_BASE_HI_BASE_IDX 0
36 …HDP_SURFACE_WRITE_FLAGS 0x00c4
37 …e regHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0
38 …HDP_SURFACE_READ_FLAGS 0x00c5
[all …]

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